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參數(shù)資料
| 型號： | K4D263238F-QC40 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL |
| 中文描述： | 100萬x 32Bit的× 4銀行雙數(shù)據(jù)速率同步DRAM的雙向數(shù)據(jù)選通和DLL |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 237K |
| 代理商： | K4D263238F-QC40 |
128M DDR SDRAM
K4D263238F
1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
- 3 -
Rev 1.1 (May 2003)
The K4D263238F is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 1,048,576 words by
32 bits, fabricated with SAMSUNG
′
s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to
2.0GB/s/chip.
I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
2.5V ± 5% power supply for device operation
2.5V ± 5% power supply for I/O interface
SSTL_2 compatible inputs/outputs
4 banks operation
MRS cycle with address key programs
-. Read latency 3 (clock)
-. Burst length (2, 4, 8 and Full page)
-. Burst type (sequential & interleave)
Full page burst length for sequential burst type only
Start address of the full page burst should be even
All inputs except data & DM are sampled at the positive
going edge of the system clock
Differential clock input
No Write Interrupted by Read function
GENERAL DESCRIPTION
FEATURES
Data I/O transactions on both edges of Data strobe
DLL aligns DQ and DQS transitions with Clock transition
Edge aligned data & data strobe output
Center aligned data & data strobe input
DM for write masking only
Auto & Self refresh
32ms refresh period (4K cycle)
100pin TQFP package
Maximum clock frequency up to 250MHz
Maximum data rate up to 500Mbps/pin
FOR 1M x 32Bit x 4 Bank DDR SDRAM
ORDERING INFORMATION
K4D263238F-UC is the Lead Free package part number.
Part NO.
Max Freq.
Max Data Rate
Interface
Package
K4D263238F-QC40
250MHz
500Mbps/pin
SSTL_2
100 TQFP
K4D263238F-QC50
200MHz
400Mbps/pin
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相關(guān)代理商/技術(shù)參數(shù) |
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| K4D263238F-QC50 | 制造商:Samsung Electro-Mechanics 功能描述:4M X 32 DDR DRAM, 0.7 ns, PQFP100 |
| K4D263238F-QC50000 | 制造商:Samsung 功能描述:DDR SGRAM X32 TQFP - Trays |
| K4D263238G-GC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit GDDR SDRAM |
| K4D263238G-GC2A | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit GDDR SDRAM |
| K4D263238G-GC33 | 制造商:Samsung Semiconductor 功能描述: |
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