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參數(shù)資料
| 型號(hào)： | K4D263238F-QC40 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL |
| 中文描述： | 100萬x 32Bit的× 4銀行雙數(shù)據(jù)速率同步DRAM的雙向數(shù)據(jù)選通和DLL |
| 文件頁數(shù)： | 10/17頁 |
| 文件大?。?/td> | 237K |
| 代理商： | K4D263238F-QC40 |
128M DDR SDRAM
K4D263238F
- 10 -
Rev 1.1 (May 2003)
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
V
IN
, V
OUT
-0.5 ~ 3.6
V
Voltage on V
DD
supply relative to Vss
V
DD
-1.0 ~ 3.6
V
Voltage on V
DD
supply relative to Vss
V
DDQ
-0.5 ~ 3.6
V
Storage temperature
T
STG
-55 ~ +150
°
C
Power dissipation
P
D
1.8
W
Short circuit current
I
OS
50
mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Note :
POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to V
SS
=0V, T
A
=0 to 65
°
C)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Device Supply voltage
V
DD
2.375
2.50
2.625
V
1
Output Supply voltage
V
DDQ
2.375
2.50
2.625
V
1
Reference voltage
V
REF
0.49*V
DDQ
-
0.51*V
DDQ
V
2
Termination voltage
Vtt
V
REF
-0.04
V
REF
V
REF
+0.04
V
3
Input logic high voltage
V
IH
V
REF
+0.15
-
V
DDQ
+0.30
V
4
Input logic low voltage
V
IL
-0.30
-
V
REF
-0.15
V
5
Output logic high voltage
V
OH
Vtt+0.76
-
-
V
I
OH
=-15.2mA
Output logic low voltage
V
OL
-
-
Vtt-0.76
V
I
OL
=+15.2mA
Input leakage current
I
IL
-5
-
5
uA
6
Output leakage current
I
OL
-5
-
5
uA
6
1. Under all conditions V
DDQ
must be less than or equal to V
DD
.
2. V
REF
is expected to equal 0.50*V
DDQ
of the transmitting device and to track variations in the DC level of the same. Peak to
peak noise on the V
REF
may not exceed +
2% of the DC value. Thus, from 0.50*V
DDQ
, V
REF
is allowed +
25mV for DC error
and an additional +
25mV for AC noise.
3. V
tt
of the transmitting device must track V
REF
of the receiving device.
4. V
IH
(max.)= V
DDQ
+1.5V for a pulse and it which can not be greater than 1/3 of the cycle rate.
5. V
IL
(min.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.
6. For any pin under test input of 0V
≤
V
IN
≤
V
DD
is acceptable. For all other pins that are not under test V
IN
=0V.
Note :
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