參數(shù)資料
型號(hào): K4D263238F-QC40
廠(chǎng)商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL
中文描述: 100萬(wàn)x 32Bit的× 4銀行雙數(shù)據(jù)速率同步DRAM的雙向數(shù)據(jù)選通和DLL
文件頁(yè)數(shù): 13/17頁(yè)
文件大小: 237K
代理商: K4D263238F-QC40
128M DDR SDRAM
K4D263238F
- 13 -
Rev 1.1 (May 2003)
1
3
4
6
7
tCL
tCK
Hi-Z
Hi-Z
CK, CK
DQS
DQ
CS
DM
2
5
tIS
tIH
8
tDS tDH
0
tRPST
tRPRE
Db0
Db1
tDQSS
tDQSH
tCH
Da1
Da2
tWPST
COMMAND
READA
WRITEB
tDQSQ
t
WPRES
t
WPREH
tDQSCK
tAC
AC CHARACTERISTICS
Simplified Timing @ BL=2, CL=3
Parameter
Symbol
-40
-50
Unit
Note
Min
4.0
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.4
0.4
tCLmin
or
tCHmin
tHP-0.4
Max
10
0.55
0.55
0.6
0.6
0.4
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
Min
5.0
0.45
0.45
-0.7
-0.7
-
0.9
0.4
0.8
0
0.25
0.4
0.4
0.4
1.0
1.0
0.45
0.45
tCLmin
or
tCHmin
tHP-0.45
Max
10
0.55
0.55
+0.7
+0.7
+0.45
1.1
0.6
1.2
-
-
0.6
0.6
0.6
-
-
-
-
CK cycle time
CK high level width
CK low level width
DQS out access time from CK
Output access time from CK
Data strobe edge to Dout edge
Read preamble
Read postamble
CK to valid DQS-in
DQS-In setup time
DQS-in hold time
DQS write postamble
DQS-In high level width
DQS-In low level width
Address and Control input setup
Address and Control input hold
DQ and DM setup time to DQS
DQ and DM hold time to DQS
CL=3
tCK
tCH
tCL
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPREH
tWPST
tDQSH
tDQSL
tIS
tIH
tDS
tDH
ns
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
ns
ns
ns
ns
1
Clock half period
tHP
-
-
ns
1
Data output hold time from DQS
tQH
-
-
ns
1
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