參數(shù)資料
型號: JS28F256P30T85
廠商: INTEL CORP
元件分類: DRAM
英文描述: Intel StrataFlash Embedded Memory
中文描述: 16M X 16 FLASH 1.8V PROM, 88 ns, PDSO56
封裝: 14 X 20 MM, LEAD FREE, TSOP-56
文件頁數(shù): 47/102頁
文件大?。?/td> 1609K
代理商: JS28F256P30T85
1-Gbit P30 Family
Datasheet
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
April 2005
47
8.3
Power Supply Decoupling
Flash memory devices require careful power supply de-coupling. Three basic power supply current
considerations are: 1) standby current levels; 2) active current levels; and 3) transient peaks
produced when CE# and OE# are asserted and deasserted.
When the device is accessed, many internal conditions change. Circuits within the device enable
charge-pumps, and internal logic states change at high speed. All of these internal activities
produce transient signals. Transient current magnitudes depend on the device outputs’ capacitive
and inductive loading. Two-line control and correct de-coupling capacitor selection suppress
transient voltage peaks.
Because Intel
Multi-Level Cell (MLC) flash memory devices draw their power from V
CC
, VPP,
and VCCQ, each power connection should have a 0.1 μF ceramic capacitor to ground. High-
frequency, inherently low-inductance capacitors should be placed as close as possible to package
leads.
Additionally, for every eight devices used in the system, a 4.7 μF electrolytic capacitor should be
placed between power and ground close to the devices. The bulk capacitor is meant to overcome
voltage droop caused by PCB trace inductance.
Figure 27.
Reset Operation Waveforms
(
A) Reset during
read mode
(B) Reset during
program or block erase
P1
P2
(C) Reset during
program or block erase
P1
P2
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
RST# [P]
RST# [P]
RST# [P]
Abort
Complete
Abort
Complete
V
CC
0V
V
CC
(D) VCC Power-up to
RST# high
P1
R5
P2
P3
P2
R5
R5
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