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參數資料
| 型號： | IX1949PA |
| 廠商： | Sharp Corporation |
| 英文描述： | Phase-Locked-Loop Integrated Circuit(鎖相環(huán)集成電路) |
| 中文描述： | 鎖相環(huán)回路集成電路（鎖相環(huán)集成電路） |
| 文件頁數： | 4/6頁 |
| 文件大?。?/td> | 43K |
| 代理商： | IX1949PA |
IX1949PA/IX2083PA-Series
SHARP IX1949PA/IX2083PA-Series . . .
4
RF Application Note
Serial Input TIming
So far, the information provided only discusses a
single PLL. Some of our satellite and cable tuners only
use a PLL for the first Local oscillator. In these cases,
the second LO is controlled by an analog voltage or
some other process.
In some tuner models for cable data receivers, both
the first and second LOs are PLL-tuned. In this case,
the step size of the second LO is smaller than for the
first LO. For the example of a crystal reference fre-
quency of 4 MHz, the divisor R used to create the 250
kHz step was 16, as shown.
To create a step size of 25 kHz from a 4 MHz crystal
the divisor would need to be 160.
This value of 160 would be the R value loaded into
the second PLL in this type of tuner.
For a different crystal reference frequency, such as
10 MHz, the value of R would change as required:
With the information shown above, programming the
IX2083PA-series of PLLs should be fairly straightfor-
ward.
For our cable television tuners that use the Toshiba
TD6359P PLL, refer to the specification for this device
or the application note for programming the VTSH-
Series tuners.
EXAMPLES
For the cable television example used above, the
expression:
(6)
1,011 MHz = [(64 × 63) + 12] × 250 kHz.
holds for all of the channels in the cable system. In
a standard channel plan.
For all of the frequencies in the sequence of chan-
nels, the relationship of LO - channel = IF applies.
For channel 2: 55.25 MHz + 955.75 MHz =
1,011 MHz.
For channel 69, it would be: 493.25 MHz +
955.75 MHz = 1,449 MHz.
16
4 MHz
250 kHz
=
16
4 MHz
25 kHz
=
400
10 MHz
25 kHz
=
CHANNEL
2
3
4
69
70
71
FREQUENCY
55.25 MHz
61.25 MHz
67.25MHz
493.25 MHz
499.25 MHz
505.25 MHz
Figure 3. Serial Input Timing
t
1
. . .
. . .
. . .
. . .
. . .
. . .
t
2
t
3
t
4
t
5
(SW 1)
S19
MSB
DATA
CLOCK
LE
(FC)
S18
S10
S9
S1
C LSB
(S8)
(S7)
(S1)
(C CONTROL BIT)
RF14-3
NOTES:
1. All times are
≥
1
μ
s.
2. Bits enclosed in parentheses are used when the Reference Divider in the Control Register
is selected. One bit of data is shifted into the shift register on the rising edge of the clock.
3. t
1
= Data Setup Time, t
2
= Data Hold Time, t
3
= Clock Pulse Width,
t
4
= LE setup time to the rising edge of the last clock, t
5
= LE Pulse Width
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