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參數(shù)資料
| 型號： | IX1949PA |
| 廠商： | Sharp Corporation |
| 英文描述： | Phase-Locked-Loop Integrated Circuit(鎖相環(huán)集成電路) |
| 中文描述： | 鎖相環(huán)回路集成電路（鎖相環(huán)集成電路） |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 43K |
| 代理商： | IX1949PA |
IX1949PA/IX2083PA-Series
SHARP IX1949PA/IX2083PA-Series . . .
2
RF Application Note
When the signal in the first IF filter at 954 MHz is
mixed with the second LO of 910 MHz, the difference
will place the output at the center of the digital IF at
44 MHz.
In both cases the numbers work out the same as
long as standard frequencies are being used. Tuning
adjustments can be made at either the first or second
LO, depending on the requirement.
For this example, the first LO or F
VCO
= 1,011 MHz,
and the expression would be:
1,011 MHz = (64N + A) × Step Size.
If the step size of this LO is 250 kHz, then the tuning
expression now looks like:
1,011 MHz = (64N + A) × 250 kHz.
By algebra we divide both sides by 250 kHz and
reduce this statement to:
In this form, we can easily determine the value of
the quantity (64N + A) for any tuned frequency. This
is fairly straightforward as the IF is a fixed value, and
the Step Size is known. The value of M = 64 is known
and is constant.
Continuing with the example, when the division on
the left hand side of the expression is performed, the
expression becomes:
4,044 = (64N + A). The Hz-based units have
dropped away and we have a numerical value that is
set equal to the expression within the parentheses.
In this series of PLL, the N value is loaded into a sep-
arate part of the register than the A value. The A value
is allowed 8 bits. The N value is allowed 11 bits, under
the conditions stated above.
In the example we are using, 4,044 = (64N + A),
does not neatly fit into the registers as provided in the
PLL. The values for N and A need to be determined.
A quick method to determine these values is to
divide 4,044 by 64:
Truncating this value and keeping the ‘63’ provides
the N value. There are two ways to get A. One method
is to multiply the remainder, 0.1875 by 64, or by multi-
plying 63 times 64 and subtracting the result from 4,044
deriving the result. Both methods are shown.
First Method
64 × 0.1875 = 12, as the remainder is a function of
64 when it is used as a divisor.
Second Method
4,044 – (63 × 64) = 4,044 – 4,032 = 12
The net result is the final expression with all of the
values:
(6)
1,011 MHz = [(64 × 63) + 12] × 250 kHz.
All of the above steps can be repeated for any crys-
tal reference frequency and step size. Some standard
examples are provided at the end of this material.
LOADING THE REGISTERS
The two registers are loaded in a similar manner,
however their lengths are different. The serial data for
controlling the tuner is loaded using a 3-wire serial data
bus structure. There are separate pins on the tuner that
correspond to the Data, Clock and Enable pins on the
PLL IC.
The same serial bus is used to load both registers in
the PLL. The condition of the C bit at the end of each
register determines which register is loaded.
Control Register
The control register is 16 bits in length. It contains
primarily the value of the reference divider R, and three
control bits. As both registers are loaded from the same
bus, the Least Significant Bit (LSB), or Control bit C is
set to a value of ‘1’.
The Band Switch bit BC is set to 0 and the Phase
Control bit FC is set to 0. The Divide prescaler bit SW is
set to 1 for the value of 64. In addition, SW is the Most
Significant Bit (MSB) of the 16-bit serial data string.
Check the tuner specification for your application to
determine the correct value R for the recommended
Step Size. The allowed value for R is 8 to 4,095. The
LSB of the data string is shown in Figure 1. The LSB of
the value for R is also placed at the left, so the LSB to
MSB direction of the entire string and its contents is
consistent.
(4)
250 kHz
1,011 MHz
(64N + A)
=
(5)
64
4,044
63.1875
=
Table 1. C Bit Conditions
CONTROL DATA
DESTINATION OF
SERIAL DATA
H
L
15 bit Latch
19 bit Latch
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