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參數(shù)資料
| 型號： | IX1949PA |
| 廠商： | Sharp Corporation |
| 英文描述： | Phase-Locked-Loop Integrated Circuit(鎖相環(huán)集成電路) |
| 中文描述： | 鎖相環(huán)回路集成電路（鎖相環(huán)集成電路） |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 43K |
| 代理商： | IX1949PA |
SHARP IX1949PA/IX2083PA-Series . . .
IX1949PA/IX2083PA-Series
RF Application Note
3
Direction
The MSB of the serial data string is loaded first, with
the LSB loaded last. Refer to the timing diagram for
additional information.
The Prescaler Divide Ratio bit settings are as follows:
The Programmable Divide register contains the data
values for N and A. This register is 20 bits in length, the
C bit is the LSB. An example of this register is shown in
Figure 2.
The divider value of the Swallow Counter A is
allowed to be from 0 to 255.
The divider value for the Programmable Divider N
may be from 16 to 2,047.
The data string is consistent in that the LSB of the A
and N values is oriented towards the LSB of the data
string. Direction of data shift is shown in Figure 2.
Table 2. Bit Settings
SW BIT
PRESCALER DIVIDE RATIO
H
L
64/65
256/257
Figure 1. Control Register Format
Figure 2. Programmable Divide Register
RF14-1
S S S S S S S S S S S S
C 1 2 3 4 5 6 7 8 9 10 11 12 BC FC SW
DIVIDE RATIO SETTING, R
LSB MSB
DIRECTION OF DATA SHIFT
CONTROL BIT = 1
(LSB)
DIVIDE RATIO SETTING = 1
(MSB)
PHASE SWITCH BIT FC = 0
BAND SWITCH BIT BC = 0
RF14-2
S S S S S S S S S S S S S S S S S S S
C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
SWALLOW COUNTER A
LSB MSB
DIRECTION OF DATA SHIFT
CONTROL BIT = 0
(LSB)
DIVIDE RATIO
LSB MSB
(MSB)
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