參數(shù)資料
型號(hào)： ISPPAC-CLK5320S-01TN64I
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 41/56頁
文件大?。?/td> 0K
描述： IC BUFFER FANOUT 20OUTPUT 64TQFP
標(biāo)準(zhǔn)包裝： 160
系列： ispClock™
類型： 時(shí)鐘發(fā)生器，扇出配送，零延遲緩沖器
PLL： 帶旁路
輸入： HSTL，LVCMOS，LVDS，LVPECL，LVTTL，SSTL
輸出： eHSTL，HSTL，LVCMOS，LVTTL，SSTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:20
差分 - 輸入:輸出： 是/無
頻率 - 最大： 267MHz
除法器/乘法器： 是/無
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（10x10）
包裝： 托盤
其它名稱： 220-1003
Lattice Semiconductor
ispClock5300S Family Data Sheet
46
Detailed Pin Descriptions
VCCO_[0..9], GNDO_[0..9] – These pins provide power and ground for each of the output banks. In the case when
an output bank is unused, its corresponding VCCO pin may be left unconnected or preferably should be tied to
ground. ALL GNDO pins should be tied to ground regardless of whether the associated bank is used or not. When
a bank is used, it should be individually bypassed with a capacitor in the range of 0.01 to 0.1F as close to its
VCCO and GNDO pins as is practical.
BANK_[0..9]A, BANK_[0..9]B – These pins provide clock output signals. The choice of output driver type (CMOS,
SSTL, etc.) may be selected on a bank-by-bank basis. The output impedance and slew rate may be selected on an
output-by-output basis.
VCCA, GNDA – These pins provide analog supply and ground for the ispClock5300S family’s internal analog cir-
cuitry, and should be bypassed with a 0.1uF capacitor as close to the pins as is practical. To improve noise immu-
nity, it is suggested that the supply to the VCCA pin be isolated from other circuitry with a ferrite bead.
VCCD, GNDD – These pins provide digital supply and ground for the ispClock5300S family’s internal digital cir-
cuitry, and should be bypassed with a 0.1uF capacitor as close to the pins as is practical. To improve noise immu-
nity it is suggested that the supply to the VCCD pins be isolated with ferrite beads.
VCCJ – This pin provides power and a reference voltage for use by the JTAG interface circuitry. It may be set to
allow the ispClock5300S family devices to function in JTAG chains operating at voltages differing from VCCD.
REFA_REFP, REFB_REFN – These input pins provide the inputs for clock signals, and can accommodate either
single ended or differential signal protocols.
REFSEL – This input pin is used to select which clock input pair (REFA or REB) is selected for use as the reference
input. When REFSEL=0, REFA is used, and when REFSEL=1, REFB is used.
VTT_REFA, VTT_REFB – These pins are used to provide a termination voltage for the reference inputs when they
are congured for SSTL or HSTL logic, and should be connected to a suitable voltage supply in those cases.
FBK – This input pin provides feedback sense of the output clock signal, and can accommodate any of the single-
ended logic types.
VTT_FBK – This pin is used to provide a termination voltage for the feedback input when it is congured for SSTL
or HSTL logic, and should be connected to a suitable voltage supply in those cases.
TDO, TDI, TCK, TMS – These pins comprise the ispClock5300S device’s JTAG interface. The signal levels for these
pins are determined by the selection of the VCCJ voltage.
LOCK – This output pin indicates that the device’s PLL is in a locked condition when it goes HIGH.
OEX, OEY – These pins are used to enable the outputs or put them into a high-impedance condition. Each output
may be set so that it is always on, always off, enabled by OEX or enabled by OEY.
PLL_BYPASS – When this pin is pulled LOW, the V-dividers are driven from the output of the device’s VCO, and
the device behaves as a phase-locked loop. When this pin is pulled HIGH, the V-dividers are driven directly from a
selected reference input, and the PLL functions are effectively bypassed.
RESET – When this pin is pulled LOW, all on-board counters are reset, and lock is lost. If the RESET pin is not
driven by an external logic it should be pulled up to VCCD through a 10kΩ resistor.
NC – These pins have no internal connection. It is recommended that they be left unconnected.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPPACCLK5320S-01TN64I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ispPAC-CLK5406D-01SN48C 功能描述:鎖相環(huán) - PLL 3.3V 6 diff. outputs RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
ispPAC-CLK5406D-01SN48I 功能描述:鎖相環(huán) - PLL 3.3V 6 diff. outputs RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
ispPAC-CLK5410D-01SN64C 功能描述:鎖相環(huán) - PLL 3.3V 10 diff. outputs RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
ispPAC-CLK5410D-01SN64I 功能描述:鎖相環(huán) - PLL 3.3V 10 diff. outputs RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
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