參數(shù)資料
型號(hào): ISPPAC-CLK5320S-01TN64I
廠商: Lattice Semiconductor Corporation
文件頁(yè)數(shù): 29/56頁(yè)
文件大?。?/td> 0K
描述: IC BUFFER FANOUT 20OUTPUT 64TQFP
標(biāo)準(zhǔn)包裝: 160
系列: ispClock™
類型: 時(shí)鐘發(fā)生器,扇出配送,零延遲緩沖器
PLL: 帶旁路
輸入: HSTL,LVCMOS,LVDS,LVPECL,LVTTL,SSTL
輸出: eHSTL,HSTL,LVCMOS,LVTTL,SSTL
電路數(shù): 1
比率 - 輸入:輸出: 2:20
差分 - 輸入:輸出: 是/無(wú)
頻率 - 最大: 267MHz
除法器/乘法器: 是/無(wú)
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 托盤
其它名稱: 220-1003
Lattice Semiconductor
ispClock5300S Family Data Sheet
35
Figure 30. PAC-Designer Design Entry Screen
In-System Programming
The ispClock5300S is an In-System Programmable (ISP) device. This is accomplished by integrating all
E
2CMOS conguration control logic on-chip. Programming is performed through a 4-wire, IEEE 1149.1 compliant
serial JTAG interface at normal logic levels. Once a device is programmed, all conguration information is stored
on-chip, in non-volatile E
2CMOS memory cells. The specics of the IEEE 1149.1 serial interface and all
ispClock5300S instructions are described in the JTAG interface section of this data sheet.
User Electronic Signature
A user electronic signature (UES) feature is included in the E
2CMOS memory of the ispClock5300S. This consists
of 32 bits that can be congured by the user to store unique data such as ID codes, revision numbers or inventory
control data. The specics this feature are discussed in the IEEE 1149.1 serial interface section of this data sheet.
Electronic Security
An electronic security “fuse” (ESF) bit is provided in every ispClock5300S device to prevent unauthorized readout
of the E
2CMOS conguration bit patterns. Once programmed, this cell prevents further access to the functional
user bits in the device. This cell can only be erased by reprogramming the device, so the original conguration can
not be examined once programmed. Usage of this feature is optional. The specics of this feature are discussed in
the IEEE 1149.1 serial interface section of this data sheet.
Production Programming Support
Once a nal conguration is determined, an ASCII format JEDEC le can be created using the PAC-Designer soft-
ware. Devices can then be ordered through the usual supply channels with the user’s specic conguration already
preloaded into the devices. By virtue of its standard interface, compatibility is maintained with existing production
programming equipment, giving customers a wide degree of freedom and exibility in production planning.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPPACCLK5320S-01TN64I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ispPAC-CLK5406D-01SN48C 功能描述:鎖相環(huán) - PLL 3.3V 6 diff. outputs RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
ispPAC-CLK5406D-01SN48I 功能描述:鎖相環(huán) - PLL 3.3V 6 diff. outputs RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
ispPAC-CLK5410D-01SN64C 功能描述:鎖相環(huán) - PLL 3.3V 10 diff. outputs RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
ispPAC-CLK5410D-01SN64I 功能描述:鎖相環(huán) - PLL 3.3V 10 diff. outputs RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray