Specifications ispLSI 2192VE 6 External Timing Parameters Over Recommended Operating Conditions tpd1
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鍨嬭櫉(h脿o)锛� ISPLSI 2192VE-180LT128
寤犲晢锛� Lattice Semiconductor Corporation
鏂囦欢闋佹暩(sh霉)锛� 12/15闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC PLD ISP 96I/O 5NS 128TQFP
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绯诲垪锛� ispLSI® 2000VE
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閭忚集鍏冧欢/閭忚集濉婃暩(sh霉)鐩細 48
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鍖呰锛� 鎵樼洡
鍏跺畠鍚嶇ū锛� ISPLSI2192VE-180LT128
Specifications ispLSI 2192VE
6
External Timing Parameters
Over Recommended Operating Conditions
tpd1
UNITS
-135
MIN.
TEST
COND.
1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
Table 2-0030B/2192VE
1
3
2
1
tsu2 + tco1
(
)
-100
MIN.
MAX.
DESCRIPTION
#
PARAMETER
A1
Data Propagation Delay, 4PT Bypass, ORP Bypass
鈥�
7.5
鈥�
10.0
ns
tpd2
A2
Data Propagation Delay
鈥�
ns
fmax
A3
Clock Frequency with Internal Feedback
135
鈥�
100
鈥�
MHz
fmax (Ext.)
鈥�4
Clock Frequency with External Feedback
鈥�
MHz
fmax (Tog.)
鈥�5
Clock Frequency, Max. Toggle
鈥�
MHz
tsu1
鈥�6
GLB Reg. Setup Time before Clock, 4 PT Bypass
鈥�
ns
tco1
A7
GLB Reg. Clock to Output Delay, ORP Bypass
鈥�
ns
th1
鈥�8
GLB Reg. Hold Time after Clock, 4 PT Bypass
0.0
鈥�
ns
tsu2
鈥�9
GLB Reg. Setup Time before Clock
6.0
鈥�
ns
tco2
A10
GLB Reg. Clock to Output Delay
鈥�
ns
th2
鈥�11
GLB Reg. Hold Time after Clock
0.0
鈥�
ns
tr1
A12
Ext. Reset Pin to Output Delay, ORP Bypass
鈥�
ns
trw1
鈥�13
Ext. Reset Pulse Duration
5.0
鈥�
ns
tptoeen
B14
Input to Output Enable
鈥�
ns
tptoedis
C15
Input to Output Disable
鈥�
ns
tgoeen
B16
Global OE Output Enable
鈥�
ns
tgoedis
C17
Global OE Output Disable
鈥�
ns
twh
鈥�18
External Synchronous Clock Pulse Duration, High
3.5
鈥�
ns
twl
鈥�19
External Synchronous Clock Pulse Duration, Low
3.5
鈥�
ns
100
143
5.0
4.0
鈥�
5.0
鈥�
9.0
鈥�
12.0
7.0
10.0
77
100
6.5
0.0
8.0
0.0
6.5
5.0
13.0
5.0
6.0
12.5
15.0
9.0
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