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參數(shù)資料
| 型號： | ISPLSI 1032E-70LTNI |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 10/17頁 |
| 文件大小： | 0K |
| 描述： | IC PLD ISP 64I/O 15NS 100TQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | ispLSI® 1000E |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時間 tpd(1)： | 15.0ns |
| 電壓電源 - 內(nèi)部： | 4.5 V ~ 5.5 V |
| 邏輯元件/邏輯塊數(shù)目： | 32 |
| 門數(shù)： | 6000 |
| 輸入/輸出數(shù)： | 64 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | 220-1596 ISPLSI 1032E-70LTNI-ND ISPLSI1032E-70LTNI |
2
Specifications ispLSI 1032E
USE
ispLSI
1032EA
FOR
NEW
DESIGNS
Functional Block Diagram
Figure 1. ispLSI 1032E Functional Block Diagram
The device also has 64 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, registered in-
put,
latched
input,
output
or
bi-directional
I/O pin with 3-state control. The signal levels are TTL
compatible voltages and the output drivers can source 4
mA or sink 8 mA. Each output can be programmed
independently for fast or slow output slew rate to mini-
mize overall output switching noise.
Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 16 universal I/O cells by the ORP. Each ispLSI
1032E device contains four Megablocks.
The GRP has, as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 1032E device are selected using the
Clock Distribution Network. Four dedicated clock pins
(Y0, Y1, Y2 and Y3) are brought into the distribution
network, and five clock outputs (CLK 0, CLK 1, CLK 2,
IOCLK 0 and IOCLK 1) are provided to route clocks to the
GLBs and I/O cells. The Clock Distribution Network can
also be driven from a special clock GLB (C0 on the ispLSI
1032E device). The logic of this GLB allows the user to
create an internal clock from a combination of internal
signals within the device.
I/O
63
I/O
62
I/O
61
I/O
60
RESET
Global
Routing
Pool
(GRP)
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
Clock
Distribution
Network
C7
C6
C5
C4
C3
C2
C1
C0
A0
A1
A2
A3
A4
A5
A6
A7
Generic
Logic Blocks
(GLBs)
Megablock
Output
Routing
Pool
(ORP)
Output
Routing
Pool
(ORP)
Output Routing Pool (ORP)
Input Bus
ispEN
lnput
Bus
lnput
Bus
I/O
59
I/O
58
I/O
57
I/O
56
I/O
55
I/O
54
I/O
53
I/O
52
I/O
51
I/O
50
I/O
49
I/O
48
IN
7
IN
6
D7
D6
D5
D4
D3
D2
D1
D0
I/O
16
I/O
17
I/O
18
I/O
19
SDO/IN
2
SCLK/IN
3
I/O
20
I/O
21
I/O
22
I/O
23
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
I/O 35
I/O 34
I/O 33
I/O 32
I/O 0
I/O 1
I/O 2
I/O 3
I/O 12
I/O 13
I/O 14
I/O 15
SDI/IN 0
MODE/IN 1
I/O 8
I/O 9
I/O 10
I/O 11
I/O 4
I/O 5
I/O 6
I/O 7
I/O 47
I/O 46
I/O 45
I/O 44
GOE 1/IN 5
GOE 0/IN 4
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
Y0
Y1
Y2
Y3
B0
B1
B2
B3
B4
B5
B6
B7
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ispLSI1032E-70LTNI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI1032E80LJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
| ISPLSI1032E-80LJ | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density Programmable Logic |
| ISPLSI1032E80LJI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ISPLSI1032E80LJN | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
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