- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19792 > ISPLSI 1024-60LJI (Lattice Semiconductor Corporation)IC PLD ISP 48I/O 20NS 68PLCC PDF資料下載
參數(shù)資料
| 型號(hào)： | ISPLSI 1024-60LJI |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLD ISP 48I/O 20NS 68PLCC |
| 標(biāo)準(zhǔn)包裝： | 18 |
| 系列： | ispLSI® 1000 |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時(shí)間 tpd(1)： | 20.0ns |
| 電壓電源 - 內(nèi)部： | 4.5 V ~ 5.5 V |
| 邏輯元件/邏輯塊數(shù)目： | 24 |
| 門數(shù)： | 4000 |
| 輸入/輸出數(shù)： | 48 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 68-PLCC（24.23x24.23） |
| 包裝： | 管件 |
| 其它名稱： | ISPLSI1024-60LJI |
ispLSI 1024
In-System Programmable High Density PLD
1
1024_06
Features
HIGH-DENSITY PROGRAMMABLE LOGIC
— High-Speed Global Interconnect
— 4000 PLD Gates
— 48 I/O Pins, Six Dedicated Inputs
— 144 Registers
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Fast Random Logic
— Security Cell Prevents Unauthorized Copying
HIGH PERFORMANCE E2CMOS TECHNOLOGY
—
fmax = 90 MHz Maximum Operating Frequency
—
fmax = 60 MHz for Industrial and Military/883 Devices
—
tpd = 12 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile E2CMOS Technology
— 100% Tested
IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP) 5-Volt Only
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
COMBINES EASE OF USE AND THE FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEX-
IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
ispDesignEXPERT – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER
— PC and UNIX Platforms
unctional
Block Diagram
Output Routing Pool
CLK
B0 B1 B2 B3 B4 B5 B6 B7
A0
A1
A2
A3
A4
A5
A6
A7
C7
C6
C5
C4
C3
C2
C1
C0
Output
Routing
Pool
Output
Routing
Pool
Global Routing Pool (GRP)
Logic
Array
DQ
GLB
0139-A-isp
Description
The ispLSI 1024 is a High-Density Programmable Logic
Device containing 144 Registers, 48 Universal I/O pins,
six Dedicated Input pins, four Dedicated Clock Input pins
and a Global Routing Pool (GRP). The GRP provides
complete interconnectivity between all of these elements.
The ispLSI 1024 features 5-Volt in-system programma-
bility and in-system diagnostic capabilities. It is the first
device which offers non-volatile reprogrammability of the
logic, as well as the interconnect to provide truly
reconfigurable systems.
The basic unit of logic on the ispLSI 1024 device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. C7 (see figure 1). There are a total of 24 GLBs in the
ispLSI 1024 device. Each GLB has 18 inputs, a program-
mable AND/OR/XOR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
other GLB on the device.
Copyright 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
February 1999
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
Functional Block Diagram
ALL
DEVICES
DISCONTINUED
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RMM36DSEH-S13 | CONN EDGECARD 72POS .156 EXTEND |
| ISPLSI 1032E-70LTNI | IC PLD ISP 64I/O 15NS 100TQFP |
| RSM36DRTN-S13 | CONN EDGECARD 72POS .156 EXTEND |
| MIC5209-2.5BS TR | IC REG LDO 2.5V .5A SOT223 |
| MIC5207-3.3BM5 TR | IC REG LDO 3.3V .18A SOT23-5 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ispLSI1024-60LJI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI1024-60LT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
| ISPLSI1024-60LTI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述: |
| ISPLSI1024-80LJ | 制造商:Lattice Semiconductor Corporation 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述:COMPLEX-EEPLD, 96-CELL, 20NS PROP DELAY, 68 Pin, Plastic, PLCC |
| ISPLSI1024-80LT | 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。