Specifications ispLSI 1024 9 Maximum GRP Delay vs GLB Loads ispLSI 1024-60 ispLSI 1024-80 ispLSI 1024-90 1 2 3 4 8 12 16 GLB Loads GRP Delay (n" />
參數(shù)資料
型號: ISPLSI 1024-60LJI
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 2/14頁
文件大?。?/td> 0K
描述: IC PLD ISP 48I/O 20NS 68PLCC
標(biāo)準(zhǔn)包裝: 18
系列: ispLSI® 1000
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1): 20.0ns
電壓電源 - 內(nèi)部: 4.5 V ~ 5.5 V
邏輯元件/邏輯塊數(shù)目: 24
門數(shù): 4000
輸入/輸出數(shù): 48
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 68-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 68-PLCC(24.23x24.23)
包裝: 管件
其它名稱: ISPLSI1024-60LJI
Specifications ispLSI 1024
9
Maximum GRP Delay vs GLB Loads
ispLSI 1024-60
ispLSI 1024-80
ispLSI 1024-90
1
2
3
4
8
12
16
GLB Loads
GRP
Delay
(ns)
4
5
6
0
0126A-80-24-isp.eps
Power Consumption
Figure 3. Typical Device Power Consumption vs fmax
ICC can be estimated for the ispLSI 1024 using the following equation:
ICC = 42 + (# of PTs * 0.45) + (# of nets * Max. freq * 0.008) where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 2 GLB loads on
average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the
program in the device, the actual ICC should be verified.
50
100
150
0
1020
3040
50
60
70
fmax (MHz)
I CC
(mA)
80
200
Notes: Configuration of Six 16-bit Counters
Typical Current at 5V, 25C
ispLSI 1024
0127A-24-80-isp
Power consumption in the ispLSI 1024 device depends
on two primary factors: the speed at which the device is
operating, and the number of Product Terms used. Fig-
ure 3 shows the relationship between power and operat-
ing speed.
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