參數(shù)資料
型號(hào): ISP1301BS
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: Universal Serial Bus On-The-Go transceiver
中文描述: LINE TRANSCEIVER, PQCC24
封裝: 4 X 4 MM, 0.85 MM HEIGHT, LEAD FREE AND HALOGEN FREE, PLASTIC, MO-220, SOT-616-1, HVQFN-24
文件頁數(shù): 22/46頁
文件大?。?/td> 245K
代理商: ISP1301BS
Philips Semiconductors
ISP1301
USB OTG transceiver
Product data
Rev. 01 — 14 April 2004
22 of 46
9397 750 11355
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Interrupt Enable High register (Set/Clear: 0EH/0FH):
The Interrupt Enable High
register enables interrupts on transition from FALSE to TRUE.
Table 31
provides the
bit allocation of this register.
11.2 Interrupts
Table 26
indicates the signals that can generate interrupts. Any of the signals given in
Table 26
can generate an interrupt when the signal becomes either LOW or HIGH.
After an interrupt has been generated, the OTG controller should be able to read the
status of each signal and the bit that indicates whether or not that signal generated
the interrupt.
A bit in the Interrupt Latch register is set when any of these occurs:
Writing logic 1 to its set address causes the corresponding bit to be set
The corresponding bit in the Interrupt Enable High register is set, and the
associated signal changes from LOW to HIGH
The corresponding bit in the Interrupt Enable Low register is set, and the
associated signal changes from HIGH to LOW.
Table 30:
Bit
7
6
5
4
3
2
1
0
Interrupt Enable Low register: bit description
Symbol
Description
CR_INT
interrupt enable for CR_INT status change from 1 to 0
BDIS_ACON
interrupt enable for BDIS_ACON status change from 1 to 0
ID_FLOAT
interrupt enable for ID_FLOAT status change from 1 to 0
DM_HI
interrupt enable for DM_HI status change from 1 to 0
ID_GND
interrupt enable for ID_GND status change from 1 to 0
DP_HI
interrupt enable for DP_HI status change from 1 to 0
SESS_VLD
interrupt enable for SESS_VLD status change from 1 to 0
VBUS_VLD
interrupt enable for VBUS_VLD status change from 1 to 0
Table 31:
Bit
Symbol
Interrupt Enable High register: bit allocation
7
6
CR_INT
BDIS_
ACON
0
0
R/S/C
R/S/C
5
4
3
2
1
0
ID_FLOAT
DM_HI
ID_GND
DP_HI
SESS_VLD
VBUS_VLD
Reset
Access
0
0
0
0
0
0
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
Table 32:
Bit
7
6
5
4
3
2
1
0
Interrupt Enable High register: bit description
Symbol
Description
CR_INT
interrupt enable for CR_INT status change from 0 to 1
BDIS_ACON
interrupt enable for BDIS_ACON status change from 0 to 1
ID_FLOAT
interrupt enable for ID_FLOAT status change from 0 to 1
DM_HI
interrupt enable for DM_HI status change from 0 to 1
ID_GND
interrupt enable for ID_GND status change from 0 to 1
DP_HI
interrupt enable for DP_HI status change from 0 to 1
SESS_VLD
interrupt enable for SESS_VLD status change from 0 to 1
VBUS_VLD
interrupt enable for VBUS_VLD status change from 0 to 1
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