
Philips Semiconductors
ISP1301
USB OTG transceiver
Product data
Rev. 01 — 14 April 2004
19 of 46
9397 750 11355
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
11.1.3
OTG registers
OTG Control register (Set/Clear: 06H/07H):
Table 21
provides the bit allocation of
the OTG Control register.
Table 19:
Bit
Symbol
Mode Control 2 register: bit allocation
7
EN2V7
PSW_OE
6
5
4
3
2
1
0
AUDIO_EN
TRANSP_
BDIR1
0
R/S/C
TRANSP_
BDIR0
0
R/S/C
BI_DI
SPD_SUSP
_CTRL
0
R/S/C
GLOBAL_
PWR_DN
0
R/S/C
Reset
Access
0
0
0
1
R/S/C
R/S/C
R/S/C
R/S/C
Table 20:
Bit
7
Mode Control 2 register: bit description
Symbol
Description
EN2V7
0 —
V
BAT
= 3.0 V to 4.5 V
1 —
V
BAT
= 2.7 V to 4.5 V
PSW_OE
0 —
ADR/PSW pin acts as an input
6
1 —
ADR/PSW pin is driven
0 —
SE receiver is enabled; cr_int detector is disabled
5
AUDIO_EN
1 —
SE receiver is turned off (pin VP = LOW, pin VM = LOW);
cr_int detector is enabled
TRANSP_BDIR[1:0] controls the direction of data transfer in the transparent
general-purpose buffer mode; see
Table 8
BI_DI
0 —
direction of DAT/VP and SE0/VM are fixed (transmit only)
4 to 3
2
1 —
direction of DAT/VP and SE0/VM are controlled by
pin OE_N/INT_N; see
Table 6
control of speed and suspend in USB modes:
1
SPD_SUSP_CTRL
0 —
controlled by pins SPEED and SUSPEND
1 —
controlled by bit SPEED_REG and bit SUSPEND_REG
of the Mode Control 1 register
GLOBAL_PWR_DN
0 —
normal operation
0
1 —
sets the ISP1301 to the power down mode
Activities on the I
2
C-bus or any OTG event can wake up the
chip; see
Section 12
Table 21:
Bit
Symbol
OTG Control register: bit allocation
7
VBUS_
CHRG
DISCHRG
0
R/S/C
6
5
4
3
2
1
0
VBUS_
VBUS_
DRV
0
R/S/C
ID_PULL
DOWN
0
R/S/C
DM_PULL
DOWN
1
R/S/C
DP_PULL
DOWN
1
R/S/C
DM_PULL
UP
0
R/S/C
DP_PULL
UP
0
R/S/C
Reset
Access
0
R/S/C