參數(shù)資料
型號(hào): ISP1160BD/01,151
廠商: ST-ERICSSON
元件分類(lèi): 總線(xiàn)控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁(yè)數(shù): 56/88頁(yè)
文件大?。?/td> 394K
代理商: ISP1160BD/01,151
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 05 — 24 December 2004
6 of 88
9397 750 13963
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
n.c.
26
-
no connection; leave this pin open
DACK_N
27
I
HC DMA acknowledge input; when not in use, this pin must
be connected to VCC via an external 10 k resistor
TEST_HIGH
28
-
this pin must be connected to VCC via an external 10 k
resistor
INT
29
O
HC interrupt output; programmable level, edge triggered
and polarity; see Section 10.4.1
n.c.
30
-
no connection; leave this pin open
n.c.
31
O
no connection; leave this pin open
RESET_N
32
I
reset input (Schmitt trigger); a LOW level produces an
asynchronous reset (internal pull-up resistor)
NDP_SEL
33
I
indicates to the HC software the Number of Downstream
Ports (NDP) present:
0 — select 1 downstream port
1 — select 2 downstream ports
only changes the value of the NDP eld in the
HcRhDescriptorA register; both ports will always be
enabled; see Section 10.3.1
(internal pull-up resistor)
EOT
34
I
DMA master device to inform the ISP1160 of end of DMA
transfer; active level is programmable; when not in use, this
pin must be connected to VCC via an external 10 k
resistor; see Section 10.4.1
DGND
35
-
digital ground
n.c.
36
-
no connection; leave this pin open
TEST_LOW
37
-
this pin must be connected to DGND via an external 10 k
resistor
n.c.
38
-
no connection; leave this pin open
TEST_LOW
39
-
this pin must be connected to DGND via a 1 M
resistor
H_WAKEUP
40
I
HC wake-up input; generates a remote wake-up from the
suspend state (active HIGH); when not in use, this pin must
be connected to DGND via an external 10 k
resistor
(internal pull-down resistor)
n.c.
41
-
no connection; leave this pin open
H_SUSPEND
42
O
HC suspend state indicator output; active HIGH
XTAL1
43
I
crystal input; connected directly to a 6 MHz crystal; when
this pin is connected to an external clock source,
pin XTAL2 must be left open
XTAL2
44
O
crystal output; connected directly to a 6 MHz crystal; when
pin XTAL1 is connected to an external clock source, this
pin must be left open
DGND
45
-
digital ground
H_PSW1_N
46
O
power switching control output for downstream port 1;
open-drain output
Table 2:
Pin description LQFP64…continued
Symbol[1]
Pin
Type
Description
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