31 FN7717.2 November 30, 2012 De vi ce Conf ig/C ontr ol 74 Output_mode_B DLL Range 0 = Fast 1 = Slow Default=’0’ DDR Enable 00h NOT r" />
參數(shù)資料
型號： ISLA212P13IRZ
廠商： Intersil
文件頁數(shù)： 25/36頁
文件大?。?/td> 0K
描述： IC ADC 12BIT SRL/SPI 72QFN
標(biāo)準(zhǔn)包裝： 1
系列： FemtoCharge™
位數(shù)： 12
采樣率（每秒）： 130M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 414mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 72-QFN（10x10）
包裝： 托盤
輸入數(shù)目和類型： *
ISLA212P
31
FN7717.2
November 30, 2012
De
vi
ce
Conf
ig/C
ontr
ol
74
Output_mode_B
DLL Range
0 = Fast
1 = Slow
Default=’0’
DDR Enable
00h
NOT reset by
Soft Reset
75-B5
Reserved
B6
Cal_status
Calibration
Done
Read Only
B7-BF
Reserved
De
vi
ce
T
es
t
C0
Test_io
Output Test Mode [7:4]
User Test Mode [2:0]
00h
Part in SDR Mode
0 = Off (Note 15)
1 = Midscale Short
2 = +FS Short
3 = -FS Short
4 = Checkerboard Output (0xAAAA, 0x5555) (Note 16)
7 = 0xFFFF, 0x0000 all on pattern (Note 17)
8 = User Pattern (1 to 8 deep, MSB Justified)
10 = Ramp
5, 6, 9, 11-15 = Reserved
Part in DDR Mode
0 = Off (Note 15)
1 = Midscale Short
2 = +FS Short16
3 = -FS Short
4 = Reserved (Note 16)
7 = Reserved (Note 17)
8 = User Pattern (1 to 4 deep, MSB Justified)
10 = Ramp
5, 6, 9, 11-15 = Reserved
Part in SDR Mode
0 = User pattern 1 only
1 = Cycle pattern 1 through 2
2 = Cycle pattern 1 through 3
3 = Cycle pattern 1 through 4
4 = Cycle pattern 1 through 5
5= Cycle pattern 1 through 6
6 = Cycle pattern 1 through7
7 = Cycle pattern 1 through 8
Part in DDR Mode
0 = User pattern 1 only
1 = Cycle pattern 1,3
2 = Cycle pattern 1,3,5
3 = Cycle pattern 1,3,5,7
4-7 = NA
C1
User_patt1_lsb
B7
B6
B5
B4
B3
B2
B1
B0
0x00
C2
User_patt1_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
C3
User_patt2_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
C4
User_patt2_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
C5
User_patt3_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
C6
User_patt3_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
C7
User_patt4_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
C8
User_patt4_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
C9
User_patt5_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
CA
User_patt5_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
CB
User_patt6_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
CC
User_patt6_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
CD
User_patt7_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
CE
User_patt7_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
CF
User_patt8_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
D0
User_patt8_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
D1-FF
Reserved
FE
Offset/Gain_Adjust_Enable
Reserved
Enable
1 = Enable
00h
FF
Reserved
NOTES:
15. During Calibration xCCCC (MSB justified) is presented at the output data bus, toggling on the LSB (and higher) data bits occurs at completion of calibration. This
behavior can be used as an option to determine calibration state.
16. Use test_io = 0x80 and User Pattern 1 = 0x9999 for Checkerboard outputs in DDR mode. In SDR mode, write ‘0x41’ to test_io for Checkerboard outputs.
17. Use test_io = 0x80 and User Pattern 1 = 0xAAAA for all ones/zeroes outputs in DDR mode. In SDR mode, write ‘0x71’ to test_io for all ones/zeros outputs.
SPI Memory Map (Continued)
ADDR.
(Hex)
PARAMETER NAME
BIT 7 (MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 (LSB)
DEF. VALUE
(HEX)
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