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參數(shù)資料
| 型號： | ISLA212P13IRZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 20/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT SRL/SPI 72QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | FemtoCharge™ |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 130M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 414mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 72-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 72-QFN（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | * |
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ISLA212P
27
FN7717.2
November 30, 2012
Bit 0 in register 0xFE must be set high to enable updates written to
0x26 and 0x27 to be used by the ADC (see description for 0xFE).
ADDRESS 0X28: GAIN_COARSE_ADC1
ADDRESS 0X29: GAIN_MEDIUM_ADC1
ADDRESS 0X2A: GAIN_FINE_ADC1
Gain of A/D core #1 can be adjusted in coarse, medium and fine
steps in the same way that core #0 can be adjusted. Coarse gain is
a 4-bit adjustment while medium and fine are 8-bit. Multiple
Coarse Gain Bits can be set for a total adjustment range of ±4.2.
Bit 0 in register 0xFE must be set high to enable updates written to
0x29 and 0x2A to be used by the ADC (see description for 0xFE).
Global Device Configuration/Control
ADDRESS 0X71: PHASE_SLIP
The output data clock is generated by dividing down the A/D input
sample clock. Some systems with multiple A/Ds can more easily latch
the data from each A/D by controlling the phase of the output data
clock. This control is accomplished through the use of the phase_slip
SPI feature, which allows the rising edge of the output data clock to be
advanced by one input clock period, as shown in Figure 42. Execution of
a phase_slip command is accomplished by first writing a '0' to bit 0 at
address 0x71, followed by writing a '1' to bit 0 at address 0x71.
ADDRESS 0X72: CLOCK_DIVIDE
The ISLA212P has a selectable clock divider that can be set to
divide by four, two or one (no division). By default, the tri-level
CLKDIV pin selects the divisor. This functionality can be
overridden and controlled through the SPI, as shown in Table 9.
This register is not changed by a Soft Reset.
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output format
of the data, as well as the logical coding. The ISLA212P can
present output data in two physical formats: LVDS (default) or
LVCMOS. Additionally, the drive strength in LVDS mode can be set
high (default, 3mA or low (2mA).
Data can be coded in three possible formats: two’s complement
(default), Gray code or offset binary. See Table 11.
This register is not changed by a Soft Reset.
ADDRESS 0X74: OUTPUT_MODE_B
Bit 6 DLL Range
This bit sets the DLL operating range to fast (default) or slow.
Internal clock signals are generated by a delay-locked loop (DLL),
which has a finite operating range. Table 12 shows the allowable
sample rate ranges for the slow and fast settings.
Bit 4 DDR Enable
Set to a ‘1’ to enable DDR.
ADDRESS 0XB6: CALIBRATION STATUS
The LSB at address 0xB6 can be read to determine calibration
status. The bit is ‘0’ during calibration and goes to a logic ‘1’
when calibration is complete. This register is unique in that it can
be read after POR at calibration, unlike the other registers on
chip, which cannot be read until calibration is complete.
DEVICE TEST
The ISLA212P can produce preset or user defined patterns on
the digital outputs to facilitate in-situ testing. A user can pick
from preset built-in patterns by writing to the output test mode
TABLE 9. CLOCK DIVIDER SELECTION
VALUE
0x72[2:0]
CLOCK DIVIDER
000
Pin Control
001
Divide by 1
010
Divide by 2
100
Divide by 4
other
Not Allowed
FIGURE 42. PHASE SLIP
ADC Input
Clock (500MHz)
Output Data
Clock (250MHz)
No clock_slip
Output Data
Clock (250MHz)
1 clock_slip
Output Data
Clock (250MHz)
2 clock_slip
2ns
4ns
2ns
TABLE 10. OUTPUT MODE CONTROL
VALUE
0x73[7:5]
OUTPUT MODE
000
LVDS 3mA (Default)
001
LVDS 2mA
100
LVCMOS
TABLE 11. OUTPUT FORMAT CONTROL
VALUE
0x73[2:0]
OUTPUT FORMAT
000
Two’s Complement (Default)
010
Gray Code
100
Offset Binary
TABLE 12. DLL RANGES
DLL RANGE
MIN
MAX
UNIT
Slow
40
100
MSPS
Fast
80
250
MSPS
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