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參數(shù)資料
| 型號： | ISL98001CQZ-240 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 2/31頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TRPL VIDEO DIGITIZER 128-MQFP |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 類型： | 視頻數(shù)字轉(zhuǎn)換器 |
| 應(yīng)用： | 數(shù)字電視，顯示器，數(shù)字 KVM，圖形處理 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-MQFP（14x20） |
| 包裝： | 托盤 |
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10
FN6148.5
September 21, 2010
Pin Descriptions
SYMBOL
MQFP PIN #(s)
DESCRIPTION
RIN1
7
Analog input. Red Channel 1. DC couple or AC couple through 0.1F.
GIN1
12
Analog input. Green Channel 1. DC couple or AC couple through 0.1F.
BIN1
19
Analog input. Blue Channel 1. DC couple or AC couple through 0.1F.
RGBGND1
13
Analog input. Ground reference for the R, G, and B inputs of channel 1 in the DC coupled configuration.
Connect to the same ground as Channel 1's R, G, and B termination resistors. This signal is not used in the
AC-coupled configuration, but the pin should still be tied to GNDA.
SOGIN1
14
Analog input. Sync on Green. Connect to GIN1 through a 0.01F capacitor in series with a 500Ω resistor.
HSYNCIN1
33
Digital input, 5V tolerant, 240mV hysteresis, 1.2k
Ω impedance to GNDA. Connect to Channel 1's HSYNC
signal through a 680
Ω series resistor.
VSYNCIN1
44
Digital input, 5V tolerant, 500mV hysteresis. Connect to Channel 1's VSYNC signal.
RIN2
22
Analog input. Red Channel 2. DC couple or AC couple through 0.1F.
GIN2
24
Analog input. Green Channel 2. DC couple or AC couple through 0.1F.
BIN2
28
Analog input. Blue Channel 2. DC couple or AC couple through 0.1F.
RGBGND2
25
Analog input. Ground reference for the R, G, and B inputs of Channel 2 in the DC coupled configuration.
Connect to the same ground as Channel 1's R, G, and B termination resistors. This signal is not used in the
AC-coupled configuration, but the pin should still be tied to GNDA.
SOGIN2
26
Analog input. Sync on Green. Connect to GIN1 through a 0.01F capacitor in series with a 500Ω resistor.
HSYNCIN2
34
Digital input, 5V tolerant, 240mV hysteresis, 1.2k
Ω impedance to GNDA. Connect to Channel 2's HSYNC
signal through a 680
Ω series resistor.
VSYNCIN2
45
Digital input, 5V tolerant, 500mV hysteresis. Connect to Channel 2's VSYNC signal.
CLOCKINVIN
41
Digital input, 5V tolerant. When high, changes the pixel sampling phase by 180°. Toggle at frame rate during
VSYNC to allow 2x undersampling to sample odd and even pixels on sequential frames. Tie to DGND if
unused.
RESET
46
Digital input, 5V tolerant, active low, 70k
Ω pullup to VD. Take low for at least 1s and then high again to reset
the ISL98001. This pin is not necessary for normal use and may be tied directly to the VD supply.
XTALIN
39
Analog input. Connect to external 24.5MHz to 27MHz crystal and load capacitor (See crystal spec for
recommended loading). Typical oscillation amplitude is 1.0VP-P centered around 0.5V.
XTALOUT
40
Analog output. Connect to external 24.5MHz to 27MHz crystal and load capacitor (See crystal spec for
recommended loading). Typical oscillation amplitude is 1.0VP-P centered around 0.5V.
XCLKOUT
47
3.3V digital output. Buffered crystal clock output at fXTAL or fXTAL/2. May be used as system clock for other
system components.
SADDR
48
Digital input, 5V tolerant. Address = 0x4C when tied low. Address = 0x4D when tied high.
SCL
50
Digital input, 5V tolerant, 500mV hysteresis. Serial data clock for 2-wire interface.
SDA
49
Bidirectional Digital I/O, open drain, 5V tolerant. Serial data I/O for 2-wire interface.
RP[7:0]
112-119
3.3V digital output. Red channel, primary pixel data. 56k pulldown when three-stated.
RS[7:0]
100-107
3.3V digital output. Red channel, secondary pixel data. 56k pulldown when three-stated.
GP[7:0]
90-97
3.3V digital output. Green channel, primary pixel data. 56k pulldown when three-stated.
GS[7:0]
80-87
3.3V digital output. Green channel, secondary pixel data. 56k pulldown when three-stated.
BP[7:0]
68-75
3.3V digital output. Blue channel, primary pixel data. 56k pulldown when three-stated.
BS[7:0]
55-62
3.3V digital output. Blue channel, secondary pixel data. 56k pulldown when three-stated.
DATACLK
121
3.3V digital output. Data clock output. Equal to pixel clock rate in 24-bit mode, one half of pixel clock rate in
48-bit mode.
DATACLK
122
3.3V digital output. Inverse of DATACLK.
HSOUT
125
3.3V digital output. HSYNC output aligned with pixel data. Use this output to frame the digital output data.
This output is always purely horizontal sync (without any composite sync signals).
ISL98001
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