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參數(shù)資料
| 型號(hào)： | ISL98001CQZ-240 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 18/31頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TRPL VIDEO DIGITIZER 128-MQFP |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 類型： | 視頻數(shù)字轉(zhuǎn)換器 |
| 應(yīng)用： | 數(shù)字電視，顯示器，數(shù)字 KVM，圖形處理 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-MQFP（14x20） |
| 包裝： | 托盤 |
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25
FN6148.5
September 21, 2010
may be significantly smaller, sometimes 300mVP-P or less.
In these cases the sync slicer will continue to operate
correctly, but the TriLevel Detect bit may not be set. Trilevel
detection accuracy can be enhanced by polling the trilevel
bit multiple times. If HSYNC is inactive, SOG is present, and
the TriLevel Sync Detect bit is read as a 1, there is a high
likelihood there is trilevel sync.
CSYNC Present
If a composite sync source (either CSYNC on HSYNC or
SOG) is selected through bits 3 and 4 of register 0x05, the
CSYNC Present bit in register 0x01 should be set. CSYNC
Present detects the presence of a low frequency, repetitive
signal inside HSYNC, which indicates a VSYNC signal. The
CSYNC Present bit should be used to confirm that the signal
being received is a reliable composite sync source.
SYNC Output Signals
The ISL98001 has 2 pairs of HSYNC and VSYNC output
signals, HSYNCOUT and VSYNCOUT, and HSOUT and
VSOUT.
HSYNCOUT and VSYNCOUT are buffered versions of the
incoming sync signals; no synchronization is done. These
signals are used for mode detection
HSOUT and VSOUT are generated by the ISL98001’s logic
and are synchronized to the output DATACLK and the digital
pixel data on the output databus. HSOUT is used to signal
the start of a new line of digital data. VSOUT is not needed in
most applications.
Both HSYNCOUT and VSYNCOUT (including the sync
separator function) remain active in power-down mode. This
allows them to be used in conjunction with the Sync Status
registers to detect valid video without powering up the
ISL98001.
HSYNCOUT
HSYNCOUT is an unmodified, buffered version of the incoming
HSYNCIN or SOGIN signal of the selected channel, with the
incoming signal’s period, polarity, and width to aid in mode
detection. HSYNCOUT will be the same format as the incoming
sync signal: either horizontal or composite sync. If a SOG input
is selected, HSYNCOUT will output the entire SOG signal,
including the VSYNC portion, pre-/post-equalization pulses if
present, and Macrovision pulses if present. HSYNCOUT
remains active when the ISL98001 is in power-down mode.
HSYNCOUT is generally used for mode detection.
VSYNCOUT
VSYNCOUT is an unmodified, buffered version of the
incoming VSYNCIN signal of the selected channel, with the
original VSYNC period, polarity, and width to aid in mode
detection. If a SOG input is selected, this signal will output
the VSYNC signal extracted by the ISL98001’s sync slicer.
Extracted VSYNC will be the width of the embedded VSYNC
pulse plus pre- and post-equalization pulses (if present).
Macrovision pulses from an NTSC DVD source will lengthen
the width of the VSYNC pulse. Macrovision pulses from
other sources (PAL DVD or videotape) may appear as a
second VSYNC pulse encompassing the width of the
Macrovision. See the Macrovision section for more
information. VSYNCOUT (including the sync separator
function) remains active in power-down mode. VSYNCOUT
is generally used for mode detection, start of field detection,
and even/odd field detection.
HSOUT
HSOUT is generated by the ISL98001’s control logic and is
synchronized to the output DATACLK and the digital pixel
data on the output databus. Its trailing edge is aligned with
pixel 0. Its width, in units of pixels, is determined by register
0x19, and its polarity is determined by register 0x18[7]. As
the width is increased, the trailing edge stays aligned with
pixel 0, while the leading edge is moved backwards in time
relative to pixel 0. HSOUT is used by the scaler to signal the
start of a new line of pixels.
The HSOUT Width register (0x19) controls the width of the
HSOUT pulse. The pulse width is nominally 1 pixel clock
period times the value in this register. In the 48 bit output
mode (register 0x18[0] = 1), or the YPbPr input mode
(register 0x05[2] = 1), the HSOUT width is incremented in 2
pixel clock (1 DATACLK) increments (see Table 8).
VSOUT
VSOUT is generated by the ISL98001’s control logic and is
synchronized to the output DATACLK and the digital pixel
data on the output databus. Its leading and trailing edges are
aligned with pixel 7 (8 pixels after HSYNC trailing edge). Its
width, in units of lines, is equal to the width of the incoming
VSYNC (See the VSYNCOUT description). Its polarity is
determined by register 0x18[6]. Note: This output is not
needed in most applications. Intersil strongly discourages
using this signal - use VSYNCOUT instead.
TABLE 8. HSOUT WIDTH
HSOUT WIDTH (PIXEL CLOCKS)
REGISTER
0x19 VALUE
24-BIT MODE,
RGB
24-BIT MODE,
YPbPr
ALL 48-BIT
MODES
00
1
0
11
1
0
22
3
2
33
3
2
44
5
4
55
5
4
66
7
6
77
7
6
ISL98001
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