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參數(shù)資料
| 型號： | ISL8705IBZT |
| 廠商： | INTERSIL CORP |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | DSP-ADDRESS SEQUENCER, PDSO14 |
| 封裝： | PLASTIC, MS-012AB, SOIC-14 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 351K |
| 代理商： | ISL8705IBZT |
3
FN9250.0
March 14, 2006
BIAS
IC Supply Current
IVIN_2.2V
VIN = 2.2V
-
191
-
A
IVIN_12V
VIN = 12V
-
246
400
A
IVIN_24V
VIN = 24V
-
286
-
A
VIN Power On Reset
VIN_POR
VIN low to high
-
2.08
2.5
V
Pin Descriptions
PINS
PIN NAME
FUNCTION DESCRIPTION
870
0
870
1
8702
8702A
870
3
870
4
870
5
NA
1
NA
1
NA
1
ENABLE#_
D
Active low open drain sequenced output. Sequenced on after ENABLE#_C and first output
to sequence off for the ISL8701, ISL8703, ISL8705. Tracks VIN upon bias.
1
NA
1
NA
1
NA
ENABLE_D Active high open drain sequenced output. Sequenced on after ENABLE_C and first output to
sequence off for the ISL8700, ISL8702, ISL8704. Pulls low with VIN < 1V.
NA
2
NA
2
NA
2
ENABLE#_
C
Active low open drain sequenced output. Sequenced on after ENABLE#_B and sequenced
off after ENABLE#_D for the ISL8701, ISL8703, ISL8705. Tracks VIN upon bias.
2
NA
2
NA
2
NA
ENABLE_C Active high open drain sequenced output. Sequenced on after ENABLE_B and sequenced
off after ENABLE_D for the ISL8700, ISL8702, ISL8704. Pulls low with VIN < 1V.
NA
3
NA
3
NA
3
ENABLE#_B Active low open drain sequenced output. Sequenced on after ENABLE#_A and sequenced
off after ENABLE#_C for the ISL8701, ISL8703, ISL8705. Tracks VIN upon bias.
3
NA
3
NA
3
NA
ENABLE_B Active high open drain sequenced output. Sequenced on after ENABLE_A and sequenced
off after ENABLE_C for the ISL8700, ISL8702, ISL8704. Pulls low with VIN < 1V.
NA
4
NA
4
NA
4
ENABLE#_A Active low open drain sequenced output. Sequenced on after CTIME period and sequenced
off after ENABLE#_B for the ISL8701, ISL8703, ISL8705. Tracks VIN upon bias.
4
NA
4
NA
4
NA
ENABLE_A Active high open drain sequenced output. Sequenced on after CTIME period and sequenced
off after ENABLE_B for the ISL8700, ISL8702, ISL8704. Pulls low with VIN < 1V.
5
OV
The voltage on this pin must be under its 1.22V Vth or the four ENABLE outputs will be
immediately pulled down. Conversely the 4 ENABLE# outputs will be released to be pulled
high via external pull ups.
6
UV
The voltage on this pin must be over its 1.22V Vth or the four ENABLE outputs will be
immediately pulled down. Conversely the 4 ENABLE# outputs will be released to be pulled
high via external pull ups.
7
GND
IC ground.
NA
8
FAULT
The VIN voltage when not within the desired UV to OV window will cause FAULT to be
released to be pulled high to a voltage equal to or less than VIN via an external resistor.
NA
9
NA
SEQ_EN
This pin provides a sequence on signal input with a high input. Internally pulled high to VIN.
NA
9
SEQ_EN#
This pin provides a sequence on signal input with a low input. Internally pulled high to VIN.
10
TIME
This pin provides a 2.6A current output so that an adjustable VIN valid to sequencing on and
off start delay period is created with a capacitor to ground.
11
TB
A resistor connected from this pin to ground determines the time delay from ENABLE_A
being active to ENABLE _B being active on turn-on and also going inactive on turn-off via the
SEQ_IN input.
12
TC
A resistor connected from this pin to ground determines the time delay from ENABLE_B
being active to ENABLE _C being active on turn-on and also going inactive on turn-off via the
SEQ_IN input.
13
TD
A resistor connected from this pin to ground determines the time delay from ENABLE_C
being active to ENABLE _D being active on turn-on and also going inactive on turn-off via the
SEQ_IN input.
14
VIN
IC Bias Pin Nominally 2.5V to 24V (12V max for ISL8702).
This pin requires a 1
F decoupling capacitor close to IC pin.
Electrical Specifications
Nominal VIN = 2.5V to +24V, TA = TJ = -40°C - 85°C, Unless Otherwise Specified.
ISL8702 VIN = 2.5V to +12V (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISL8700, ISL8701, ISL8702, ISL8703, ISL8704, ISL8705
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