參數(shù)資料
型號: ISL8705IBZT
廠商: INTERSIL CORP
元件分類: 數(shù)字信號處理外設
英文描述: DSP-ADDRESS SEQUENCER, PDSO14
封裝: PLASTIC, MS-012AB, SOIC-14
文件頁數(shù): 2/12頁
文件大?。?/td> 351K
代理商: ISL8705IBZT
10
FN9250.0
March 14, 2006
Application Concerns and Recommendations
Best practices VIN decoupling is required, a 1F capacitor is
recommended.
Coupling from the ENABLE_X pins to the sensitive UV and
OV pins can cause false OV/UV events to be detected. This
is most relevant for ISL8700, ISL8702, ISL8704 parts due to
the ENABLEA and OV pins being adjacent. This coupling
can be reduced by adding a ground trace between UV and
the ENABLE/FAULT signals, as shown in Figure 15. The
PCB traces on OV and UV should be kept as small as
practical and the ENABLE_X and FAULT traces should
ideally not be routed under/over the OV/UV traces on
different PCB layers unless there is a ground or power plane
in between. Other methods that can be used to eliminate this
issue are by reducing the value of the resistors in the
network connected to UV and OV (R2, R3, R5 in Figure 16)
or by adding small decoupling capacitors to OV and UV (C2
and C7 in Figure 16). Both these methods act to reduce the
AC impedance at the nodes, although the latter method acts
to filter the signals which will also cause an increase in the
time that a UV/OV fault takes to be detected
.
When the ISL870X is implemented on a hot swappable card
that is plugged into an always powered passive back plane
an RC filter is required on the VIN pin to prevent a high dv/dt
transient. With the already existing 1
F decoupling capacitor
the addition of a small series R (>50
) to provide a time
constant >50
s is all that is necessary.
Only the ISL8702 has a VIN limitation of 14V maximum.
FIGURE 14. OV & UV TRANSIENT IMMUNITY
8s/DIV
FAULT = LOW
VMONITOR OV
VMONITOR UV
FIGURE 15. LAYOUT DETAIL OF GND BETWEEN PINS 4 & 5
PIN 4
PIN 5
GND
ISL8700, ISL8701, ISL8702, ISL8703, ISL8704, ISL8705
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