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參數(shù)資料
| 型號： | ISL6559CBZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Multi-Phase PWM Controller |
| 中文描述： | SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | LEAD FREE, PLASTIC, MS-013-AE, SOIC-28 |
| 文件頁數(shù)： | 10/21頁 |
| 文件大?。?/td> | 606K |
| 代理商： | ISL6559CBZ |
10
FN9084.8
December 29, 2004
sources, amplifiers and the reference so that the output
voltage remains within the specified system tolerance of
±
1
% over temperature.
LOAD-LINE REGULATION
Microprocessor load current demands change from near no-
load to full load often during operation. The resulting sizable
transient current slew rate causes an output voltage spike
since the converter is not able to respond fast enough to the
rapidly changing current demands. The magnitude of the
spike is dictated by the ESR and ESL of the output
capacitors selected. In order to drive the cost of the output
capacitor solution down, one commonly accepted approach
is active voltage positioning. By adding a well controlled
output impedance, the output voltage can effectively be level
shifted in a direction which works against the voltage spike.
The average current of all the active channels, I
AVG
, flows
out IOUT, see Figure 5. IOUT is connected to FB through a
load-line regulation resistor, R
FB
. The resulting voltage drop
across R
FB
is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined as
In most cases, each channel uses the same R
ISEN
value to
sense current. A more complete expression for V
DROOP
is
derived by combining equations 3 and 4.
Droop is an optional feature of the ISL6559. If active voltage
positioning is not required, simply leave the IOUT pin open.
REFERENCE OFFSET
Typical microprocessor tolerance windows are centered
around a nominal DAC set point. Implementing a load-line
would require offsetting the output voltage above this
nominal DAC set point. Centering the load-line within the
static specification window. The ISL6559 features an internal
100
μ
A current source which feeds out the OFS pin. Placing
a resistor from OFS and ground allows the user to set the
amount of positive offset desired directly to the reference
voltage. The voltage developed across the OFS resistor,
R
OFS
, is divided down internally by a factor of 10 and directly
counters the DAC voltage at the error amplifier non-inverting
input. Select the resistor value based on the voltage offset
desired, V
OFS
, using Equation 6.
DYNAMIC VID
Next generation microprocessors can change VID inputs at
any time while the regulator is in operation. The power
management solution is required to monitor the DAC inputs
and respond to VID voltage transitions or ‘on-the-fly’ VID
changes, in a controlled manner. Supervising the safe output
voltage transition within the DAC range of the processor
without discontinuity or disruption.
The ISL6559 checks the five VID inputs at the beginning of
each channel-1 switching cycle. If the VID code has
changed, the controller waits one complete switching cycle
to validate the new code. If the VID code is stable for this
entire switching cycle, then the controller will begin executing
the output voltage change. The controller begins
incrementing the reference voltage by making 25mV steps
every two switching cycles until it reaches the new VID code.
The total time required for a VID change, t
DV
, is dependent
on the switching frequency (f
S
), the size of the change
(
VID), and the time before the next switching cycle begins.
Since the ISL6559 recognizes VID-code changes only at the
beginning of switching cycles, up to one full cycle may pass
before a VID change registers. This is followed by a one-
cycle wait before the output voltage begins to change. The
one-cycle uncertainty in Equation 8 is due to the possibility
that the VID code change may occur up to one full cycle
before being recognized.
The time required for a converter running with f
S
= 500kHz to
make a 1.2V to 1.4V reference-voltage change is between
30
μ
s and 32
μ
s as calculated using Equation 8. This example
is also illustrated in Figure 7.
V
DROOP
I
AVG
R
FB
=
(EQ. 5)
V
DROOP
I
---N
r
ISEN
)
-R
FB
=
(EQ. 6)
R
OFS
V
10
μ
A
----100
=
(EQ. 7)
f
S
-1
0.025
1
–
t
DV
f
S
-1
0.025
≤
<
(EQ. 8)
FIGURE 6. DYNAMIC-VID WAVEFORMS FOR 500KHZ
ISL6559 BASED MULTI-PHASE BUCK
CONVERTER
5
μ
s/DIV
V
REF
, 100mV/DIV
V
OUT
, 100mV/DIV
1.2V
V
ID
, 5V/DIV
01110
00110
1.2V
VID CHANGE OCCURS
ANYWHERE HERE
ISL6559
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| ISL6559CB-T | Multi-Phase PWM Controller |
| ISL6559CR-T | Multi-Phase PWM Controller |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISL6559CBZ-T | 功能描述:電流型 PWM 控制器 2 TO 4 PHS BUCK CNTRLR 2 8LD RoHS:否 制造商:Texas Instruments 開關(guān)頻率:27 KHz 上升時(shí)間: 下降時(shí)間: 工作電源電壓:6 V to 15 V 工作電源電流:1.5 mA 輸出端數(shù)量:1 最大工作溫度:+ 105 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSSOP-14 |
| ISL6559CR | 功能描述:IC REG CTRLR BUCK PWM VM 32-QFN RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標(biāo)準(zhǔn)包裝:4,000 系列:- PWM 型:電壓模式 輸出數(shù):1 頻率 - 最大:1.5MHz 占空比:66.7% 電源電壓:4.75 V ~ 5.25 V 降壓:是 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:-40°C ~ 85°C 封裝/外殼:40-VFQFN 裸露焊盤 包裝:帶卷 (TR) |
| ISL6559CR-T | 功能描述:IC REG CTRLR BUCK PWM VM 32-QFN RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標(biāo)準(zhǔn)包裝:4,000 系列:- PWM 型:電壓模式 輸出數(shù):1 頻率 - 最大:1.5MHz 占空比:66.7% 電源電壓:4.75 V ~ 5.25 V 降壓:是 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:-40°C ~ 85°C 封裝/外殼:40-VFQFN 裸露焊盤 包裝:帶卷 (TR) |
| ISL6559CRZ | 功能描述:電流型 PWM 控制器 2 TO 4 PHS BUCK CNTRLR 32L 5X5 MLFP RoHS:否 制造商:Texas Instruments 開關(guān)頻率:27 KHz 上升時(shí)間: 下降時(shí)間: 工作電源電壓:6 V to 15 V 工作電源電流:1.5 mA 輸出端數(shù)量:1 最大工作溫度:+ 105 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSSOP-14 |
| ISL6559CRZR5265 | 功能描述:IC REG CTRLR BUCK PWM VM 32-QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:275kHz 占空比:50% 電源電壓:18 V ~ 110 V 降壓:無 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR) |
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