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1
FN9084.8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002-2004. All Rights Reserved.
Dynamic VID is a trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners.
ISL6559
Multi-Phase PWM Controller
The ISL6559 provides core-voltage regulation by driving 2 to
4 interleaved synchronous-rectified buck-converter channels
in parallel. Interleaving the channel timing results in
increased ripple frequency which reduces input and output
ripple currents. The reduction in ripple results in lower
component cost, reduced dissipation, and a smaller
implementation area.
The ISL6559 uses cost and space-saving r
DS(ON)
sensing
for channel current balance, active voltage positioning, and
over-current protection. Output voltage is monitored by an
internal differential remote sense amplifier. A high-bandwidth
error amplifier drives the output voltage to match the
programmed 5-bit DAC reference voltage. The resulting
compensation signal guides the creation of pulse width
modulated (PWM) signals to control companion Intersil
MOSFET drivers. The OFS pin allows direct offset of the
DAC voltage from 0V to 50mV using a single external
resistor. The entire system is trimmed to ensure a system
accuracy of ±
1
% over temperature.
Outstanding features of this controller IC include
Dynamic VID
TM
technology allowing seamless on-the-fly VID
changing without the need of any external components.
Output voltage “droop” or active voltage positioning is
optional. When employed, it allows the reduction in size and
cost of the output capacitors required to support load
transients. A threshold-sensitive enable input allows the use
of an external resistor divider for start-up coordination with
Intersil MOSFET drivers or any other devices powered from
a separate supply.
Superior over-voltage protection is achieved by gating on the
lower MOSFET of all phases to crowbar the output voltage.
An optional second crowbar on V
IN
, formed with an external
MOSFET or SCR gated by the OVP pin, is triggered when
an over-voltage condition is detected. Under-voltage
conditions are detected, but PWM operation is not disrupted.
Over-current conditions cause a hiccup-mode response as
the controller repeatedly tries to restart. After a set number
of failed startup attempts, the controller latches off. A power
good logic signal indicates when the converter output is
between the UV and OV thresholds.
Features
Multi-Phase Power Conversion
- 2, 3 or 4 Phase Operation
Active Channel Current Balancing
Precision r
DS(ON)
Current Sharing
- Lossless
- Low Cost
Input Voltage: 12V or 5V Bias
Precision CORE Voltage Regulation
- ±
1
% System Accuracy Over Temperature
- Differential Remote Output Voltage Sensing
- Programmable Reference Offset
Microprocessor Voltage Identification Input
- 5-Bit VID Input
- 0.800V to 1.550V in 25mV Steps
- Dynamic VID Technology
Programmable Droop Voltage
Fast Transient Recovery Time
Over Current Protection
Digital Soft Start
Threshold Sensitive Enable Input
High Ripple Frequency (160kHz to 4MHz)
QFN Package:
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Package Outline
- Near Chip Scale Package footprint, which improves PCB
efficiency and has a thinner profile
Pb-Free Available (RoHS Compliant)
Applications
AMD Hammer Family Processor Voltage Regulator
Low Output Voltage, High Current DC-DC Converters
Voltage Regulator Modules
Pinouts
ISL6559CR (32 LEAD QFN)
TOP VIEW
ISL6559CB (28 LEAD SOIC)
TOP VIEW
GND
OVP
VID4
VID3
FB
IOUT
VDIFF
VSEN
RGND
EN
ISEN4
PWM4
PGOOD
ISEN3
GND
PWM3
VCC
GND
FS/DIS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
OFS
VID2
COMP
PWM1
ISEN2
VID1
VID0
ISEN1
PWM2
V
32 31 30 29 28 27 26 25
N
V
O
G
E
F
P
I
V
NC = NO CONNECT
V
R
G
G
V
P
VID2
VID1
VID0
NC
OFS
COMP
FB
NC
ISEN4
ISEN1
PWM1
PWM2
GND
ISEN2
ISEN3
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
24
23
22
21
20
19
18
17
PWM4
Data Sheet
December 29, 2004