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參數(shù)資料
| 型號： | ISL6161CB-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 5/11頁 |
| 文件大小： | 215K |
| 描述： | IC CTRLR PWR DISTRIB DUAL 14SOIC |
| 標準包裝： | 2,500 |
| 類型： | 熱交換控制器 |
| 應用： | 通用型，PCI Express? |
| 內(nèi)部開關(guān)： | 無 |
| 電源電壓： | 10.5 V ~ 13.2 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 14-SOICN |
| 包裝： | 帶卷 (TR) |
5
FN9104.4
October 2, 2008
ISL6161 Description and Operation
The ISL6161 is a multi-featured +12V and +3.3V dual power
supply distribution controller. Its features include programmable
current regulation (CR) limiting and time to latch off.
At turn-on, the gate capacitor of each external N-Channel
MOSFET is charged with a 10礎(chǔ) current source. These
capacitors create a programmable ramp (soft turn-on). A
charge pump supplies the gate drive for the 12V supply control
FET switch driving that gate to 17V.
The load currents pass through two external current sense
resistors. When the voltage across either resistor quickly
exceeds the user programmed Current Regulation voltage
threshold (CRVth) level, the controller enters current regulation.
The CRVth is set by the external resistor value on R
ILIM
pin. At
this time, the time-out capacitor, C
TIM
, starts charging with a
10礎(chǔ) current source and the controller enters the time-out
period. The length of the time-out period is set by the single
external capacitor (see Table 2) placed from the C
TIM
pin
(pin 10) to ground and is characterized by a lowered gate drive
voltage to the appropriate external N-Channel MOSFET. Once
C
TIM
charges to 2V, an internal comparator is tripped resulting
in both N-Channel MOSFETs being latched off. If the voltage
across the sense resistors rises slowly in response to an OC
condition, then the CR mode is entered at ~95% of the
programmed CR level. This difference is due to the necessary
hysteresis and response time in the CR control circuitry.
Table 1 shows R
SENSE
and R
ILIM
recommendations and
resulting CR level for the PCI-Express add-in card connector
sizes specified.
?% Current Limit Response Time
(Current within 1% of Regulated Value)
200% Current Overload, R
ILIM
= 10k?
R
SHORT
= 2.5?/DIV>
-
10
-
祍
Response Time To Dead Short
RT
SHORT
C
VG
= 0.01礔
-
500
ns
Gate Turn-On Time
t
ON3V
C
VG
= 0.01礔
-
5
-
ms
Gate Turn-On Current
I
ON3V
C
VG
= 0.01礔
8
10
12
礎(chǔ)
3x Gate Discharge Current
3xdisI
C
VG
= 0.01礔, ENABLE = Low
0.75
-
A
3.3V Undervoltage Threshold
3.3V
VUV
2.7
2.85
3.0
V
3.3VG High Voltage
3VG
11.2
11.9
-
V
SUPPLY CURRENT AND IO SPECIFICATIONS
V
DD
Supply Current
I
VDD
4
8
10
mA
V
DD
POR Rising Threshold
9.5
10.0
10.7
V
V
DD
POR Falling Threshold
9.0
9.4
9.8
V
Current Limit Time-Out
t
ILIM
C
TIM
= 0.1礔
-
20
-
ms
ENABLE
Pull-up Voltage
PWRN_V ENABLE
pin open
1.8
2.4
3.2
V
ENABLE
Rising Threshold
PWR_Vth
1.1
1.5
2
V
ENABLE
Hysteresis
PWR_hys
0.1
0.2
0.3
V
ENABLE
Pull-Up Current
PWRN_I
60
80
100
礎(chǔ)
Current Limit Time-Out Threshold (C
TIM
)
C
TIM
_Vth
1.8
2
2.2
V
C
TIM
Charging Current
C
TIM
_I
8
10
12
礎(chǔ)
C
TIM
Discharge Current
C
TIM
_disI
1.7
2.6
3.5
mA
C
TIM
Pull-Up Current
C
TIM
_disI V
CTIM
= 8V
3.5
5
6.5
mA
R
ILIM
Pin Current Source Output
R
ILIM
_Io
90
100
110
礎(chǔ)
Charge Pump Output Current
Qpmp_Io C
PUMP
= 0.1礔, C
PUMP
= 16V
320
560
900
礎(chǔ)
Charge Pump Output Voltage
Qpmp_Vo No load
17.2
17.4
-
V
Charge Pump Output Voltage - Loaded
Qpmp_VIo Load current = 100礎(chǔ)
16.2
16.7
-
V
Charge Pump POR Rising Threshold
Qpmp + Vth
15.6
16
16.5
V
Charge Pump POR Falling Threshold
Qpmp - Vth
15.2
15.7
16.2
V
Electrical Specifications V
DD
= 12V, C
VG
= 0.01礔, C
TIM
= 0.1礔, R
SENSE
= 0.1? C
BULK
= 220礔, ESR = 0.5? T
A
= T
J
= -40癈 to
+85癈, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25癈,
unless otherwise specified. Temperature limits established by characterization and are not
production tested. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ISL6161
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