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參數(shù)資料
| 型號(hào)： | ISL5929INZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 8/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT CMOS DUAL 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 274mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP（7x7） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | * |
| 采樣率（每秒）： | 150M |
4
Pin Descriptions
PIN NO.
PIN NAME
PIN DESCRIPTION
11, 19, 26
AGND
Analog ground.
13, 24
AVDD
Analog supply (+2.7V to +3.6V).
28
CLK
Clock Iinput.
27
DGND
Connect to digital ground.
10
DVDD
Digital supply (+2.7V to +3.6V).
20
FSADJ
Full scale current adjust. Use a resistor to ground to adjust full scale output current. Full scale output
current = 32 x VFSADJ/RSET.
14, 23
NC
Not internally connected. Recommend no connect.
12, 25
ICOMP, QCOMP
Compensation pin for internal bias generation. Each pin should be individually decoupled to AGND with
a 0.1
F capacitor.
1-8, 29-48
ID13-ID0, QD13-QD0 Digital data input ports. Bit 13 is most significant bit (MSB) and bit 0 is the least significant bit (LSB).
15, 22
IOUTA, QOUTA
Current outputs of the device. Full scale output current is achieved when all input bits are set to binary 1.
16, 21
IOUTB, QOUTB
Complementary current outputs of the device. Full scale output current is achieved on the complementary
outputs when all input bits are set to binary 0.
17
REFIO
Reference voltage input if Internal reference is disabled. The internal reference is not intended to drive an
external load. Use 0.1
F cap to ground when internal reference is enabled.
18
REFLO
Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable internal reference.
9
SLEEP
Connect to digital ground or leave floating for normal operation. Connect to DVDD for sleep mode.
ISL5929
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