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參數(shù)資料
| 型號(hào)： | ISL51002CQZ-110 |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 13/33頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FRONT END 10BIT VID 128-MQFP |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 位數(shù)： | 10 |
| 通道數(shù)： | 3 |
| 功率（瓦特）： | 1.2W |
| 電壓 - 電源，模擬： | 1.8V，3.3V |
| 電壓 - 電源，數(shù)字： | 1.8V，3.3V |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-MQFP（14x20） |
| 包裝： | 托盤 |
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20
FN6164.3
February 29, 2012
0x44
VSYNC Period MSB,
(read only)
3:0
VSYNC Period MSB
These bits report a 12-bit value containing the width of one frame
(= 2 fields for interlaced, = 1 field for progressive) of video.
VSYNC period for measured channel =
256*VSYNC Period MSB + VSYNC Period LSB
Units are either number of HSYNC periods or number of
fCRYSTAL/512 periods, depending on setting of VSYNC Units
register.
0x45
VSYNC Period LSB,
(read only)
7:0
VSYNC Period LSB
0x46
VSYNC Width,
(read only)
6:0
VSYNC Width
This register reports a 7-bit value containing the width the
VSYNC pulse. The value returned is for true VSYNC only: it
does not include serrations, EQ pulses, Macrovision pulses,
etc. Units are either number of HSYNC periods or number of
fCRYSTAL/512 periods, depending on setting of VSYNC Units
register.
0x47
DE Start MSB, (0x00)
1:0
DE Start MSB
10-bit value containing the number of pixel clocks between the
trailing edge of HSOUT and the first valid pixel. SXGA default
values.
0x48
DE Start LSB, (0xF6)
7:0
DE Start LSB
0x49
DE Width MSB, (0x05)
3:0
DE Width MSB
12-bit value containing the number of visible image pixels.
SXGA default values.
0x4A
DE Width LSB, (0x00)
7:0
DE Width LSB
0x4B
Line Start MSB, (0x00)
1:0
Line Start MSB
10-bit value containing the number of lines between the trailing
edge of VSYNCOUT and the first valid line. SXGA default
values.
0x4C
Line Start LSB, (0x26)
7:0
Line Start LSB
0x4D
Line Width MSB, (0x04)
3:0
Line Width MSB
12-bit value containing the number of visible lines.
SXGA default values.
0x4E
Line Width LSB, (0x00)
7:0
Line Width LSB
0x4F
Measurement Configuration,
(0x00)
0
VSYNC Units
0: VSYNC measurement reported in units of lines
(HSYNC periods)
1: VSYNC measurement reported in units of 512 crystal clock
periods
1
VSYNC_Linecount_Mode
0: New method (Integer count of HSOUTs)
1: Old method (Time measurement with rounding errors)
AUTO ADJUST REGISTERS
0x50
Phase ADJ CMD FN, (0x00)
2:0
PADJ Function
Note: A write to this register executes the command contained
in the three LSBs of the word written. Commands:
000: Reserved
001: Reserved
010: Reserved
011: SetPhase
100: Set DE
101: Reserved
110: Reserved
111: Reserved
0x51
Phase ADJ STATUS,
(read only)
7
PADJ Busy
0: Phase Adjustment function idle
1: Phase Adjustment in progress
Register Listing (Continued)
ADDRESS
REGISTER
(DEFAULT VALUE)
BITS
FUNCTION NAME
DESCRIPTION
ISL51002
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參數(shù)描述 |
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| ISL51002CQZ-150 | 制造商:Intersil Corporation 功能描述:AFE VID 3ADC 10-BIT 1.8V/3.3V 128MQFP EP - Trays 制造商:Intersil 功能描述:10 BIT VID AFE MEASURE&AUTO-ADJUST 制造商:Intersil Corporation 功能描述:10-Bit Video Analog Front End (AFE) with Measurement and Auto-Adjust Features |
| ISL51002CQZ-165 | 功能描述:IC FRONT END 10BIT VID 128-MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| ISL51002EVALZ | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:10-Bit Video Analog Front End (AFE) with Measurement and Auto-Adjust Features |
| ISL51002-EVALZ | 功能描述:EVAL BOARD FOR ISL51002 RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:* 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電源管理，電池充電器 嵌入式:否 已用 IC / 零件:MAX8903A 主要屬性:1 芯鋰離子電池 次要屬性:狀態(tài) LED 已供物品:板 |
| ISL5100A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Quad 18V Pin Electronics Driver/Window Comparator |
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