7 FN8273.1 September 5, 2013 Offset Error Matching -2 2 LSB PSRR Power Sup" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� ISL26323FBZ
寤犲晢锛� Intersil
鏂囦欢闋佹暩(sh霉)锛� 21/23闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC ADC 12BIT SPI/SRL 250K 8SOIC
妯欐簴鍖呰锛� 980
浣嶆暩(sh霉)锛� 12
閲囨ǎ鐜囷紙姣忕锛夛細 250k
鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� 涓茶锛孲PI?
杞夋彌鍣ㄦ暩(sh霉)鐩細 1
鍔熺巼鑰楁暎锛堟渶澶э級锛� 80mW
闆诲闆绘簮锛� 鍠浕婧�
宸ヤ綔婧害锛� -40°C ~ 125°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 8-SOIC锛�0.154"锛�3.90mm 瀵級
渚涙噳鍟嗚ō鍌欏皝瑁濓細 8-SOIC
鍖呰锛� 绠′欢
杓稿叆鏁�(sh霉)鐩拰椤炲瀷锛� 2 鍊嬪柈绔�锛屽柈妤�
ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329
7
FN8273.1
September 5, 2013
Offset Error Matching
-2
2
LSB
PSRR
Power Supply Rejection Ratio
70
dB
DYNAMIC PERFORMANCE
SNR
Signal-to-Noise
Notes: VIN = FS - 0.1dB, fIN = 10kHz
Differential Inputs
73.4
dB
Single-Ended Inputs
73.4
dB
SINAD
Signal-to-Noise + Distortion
Notes: VIN = FS - 0.1dB, fIN = 10kHz
Differential Inputs
73.1
dB
Single-Ended Inputs
73.1
dB
THD
Total Harmonic Distortion
Notes: VIN = FS - 0.1dB, fIN = 10kHz
Differential Inputs
-86
dB
Single-Ended Inputs
-86
dB
SFDR
Spurious-free Dynamic Range
Notes: VIN = FS - 0.1dB
fIN = 20kHz
96
dB
BW
-3dB Input Bandwidth
2.5
MHz
tAD
Sampling Aperture Delay
12
ns
tjit
Sampling Aperture Jitter
25
ps
POWER SUPPLY REQUIREMENTS
VDD
Supply Voltage
2.7
5.25
V
IDD
Supply Current
3
3.5
mA
PD
Power Consumption
Normal Operation
15
17.5
mW
IPD
Power-down Current
Auto Power-Down Mode
8
50
A
Istby
Standby Mode Current
Auto Sleep Mode
0.4
mA
DIGITAL INPUTS
VIH
0.7 VDD
V
VIL
0.2 VDD
V
VOH
IOH = -1mA
VDD-0.4
V
VOL
IOL = 1mA
0.2 VDD
V
IIH, IIL
Input Leakage Current
-100
100
nA
Serial Clock Frequency
20
MHz
TIMING SPECIFICATIONS (Note 7)
tSCLK
SCLK Period (in RAC Mode)
50
ns
tSCLK
SCLK Period (in RSC, RDC Modes)
50
100
ns
tDATA
Safe Data Transfer Time After Conversion
State Begins
1.6
s
tCSB_SCLK CSB Falling Low to SCLK Rising Edge
40
ns
tSDI_SU SDI Setup Time with Respect to Positive
Edge of SCLK
10
ns
tSDI_H
SDI Hold Time with Respect to Positive
Edge of SCLK
10
ns
tSDO_V
SDOUT Valid Time with Respect to
Negative Edge of SCLK
25
ns
tSDOZ_D SDOUT to High Impedance State After CNV
Rising Edge (or last SCLK falling edge)
(Note 8)
85
ns
tACQ
Acquisition Time when Fully Powered Up
400
ns
Electrical Specifications VREF = VDD V, VDD = 2.7V to 5V, VCM = VDD/2, SCLK = 20MHz and TA = -40掳C to +125掳C (typical performance
at +25掳C), unless otherwise specified. Boldface limits apply over the operating temperature range, -40掳C to +125掳C. (Continued)
SYMBOL
PARAMETER
TEST LEVEL OR NOTES
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
鐩搁棞PDF璩囨枡
PDF鎻忚堪
VE-21R-MX-F3 CONVERTER MOD DC/DC 7.5V 75W
MS27466E11F4P CONN RCPT 4POS WALL MT W/PINS
MS3120E16-8P CONN RCPT 8POS WALL MNT W/PINS
VI-24X-IU-F2 CONVERTER MOD DC/DC 5.2V 200W
XRT73L04BIV IC LIU E3/DS3/STS-1 4CH 144LQFP
鐩搁棞浠ｇ悊鍟�/鎶€琛撳弮鏁�(sh霉)
鍙冩暩(sh霉)鎻忚堪
ISL26323FBZ-T 鍔熻兘鎻忚堪:IC ADC 12BIT SPI/SRL 250K 8SOIC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃暩(sh霉)杞夋彌鍣� 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷撴ā濉�:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯欐簴鍖呰:250 绯诲垪:- 浣嶆暩(sh霉):12 閲囨ǎ鐜囷紙姣忕锛�:1.8M 鏁�(sh霉)鎿�(j霉)鎺ュ彛:骞惰伅(li谩n) 杞夋彌鍣ㄦ暩(sh霉)鐩�:1 鍔熺巼鑰楁暎锛堟渶澶э級:1.82W 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:48-LQFP 渚涙噳鍟嗚ō鍌欏皝瑁�:48-LQFP锛�7x7锛� 鍖呰:绠′欢 杓稿叆鏁�(sh霉)鐩拰椤炲瀷:2 鍊嬪柈绔�锛屽柈妤�
ISL26323FBZ-T7A 鍔熻兘鎻忚堪:IC ADC 12BIT SPI/SRL 250K 8SOIC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃暩(sh霉)杞夋彌鍣� 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷撴ā濉�:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯欐簴鍖呰:250 绯诲垪:- 浣嶆暩(sh霉):12 閲囨ǎ鐜囷紙姣忕锛�:1.8M 鏁�(sh霉)鎿�(j霉)鎺ュ彛:骞惰伅(li谩n) 杞夋彌鍣ㄦ暩(sh霉)鐩�:1 鍔熺巼鑰楁暎锛堟渶澶э級:1.82W 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:48-LQFP 渚涙噳鍟嗚ō鍌欏皝瑁�:48-LQFP锛�7x7锛� 鍖呰:绠′欢 杓稿叆鏁�(sh霉)鐩拰椤炲瀷:2 鍊嬪柈绔紝鍠サ
ISL26324 鍒堕€犲晢:INTERSIL 鍒堕€犲晢鍏ㄧū:Intersil Corporation 鍔熻兘鎻忚堪:12-bit, 250kSPS Low-power ADCs with Single-ended and Differential Inputs and Multiple Input Channels
ISL26324FVZ 鍔熻兘鎻忚堪:IC ADC 12BIT SPI/SRL 16-TSSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃暩(sh霉)杞夋彌鍣� 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷撴ā濉�:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯欐簴鍖呰:250 绯诲垪:- 浣嶆暩(sh霉):12 閲囨ǎ鐜囷紙姣忕锛�:1.8M 鏁�(sh霉)鎿�(j霉)鎺ュ彛:骞惰伅(li谩n) 杞夋彌鍣ㄦ暩(sh霉)鐩�:1 鍔熺巼鑰楁暎锛堟渶澶э級:1.82W 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:48-LQFP 渚涙噳鍟嗚ō鍌欏皝瑁�:48-LQFP锛�7x7锛� 鍖呰:绠′欢 杓稿叆鏁�(sh霉)鐩拰椤炲瀷:2 鍊嬪柈绔�锛屽柈妤�
ISL26324FVZ-T 鍔熻兘鎻忚堪:IC ADC 12BIT SPI/SRL 16-TSSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃暩(sh霉)杞夋彌鍣� 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷撴ā濉�:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯欐簴鍖呰:250 绯诲垪:- 浣嶆暩(sh霉):12 閲囨ǎ鐜囷紙姣忕锛�:1.8M 鏁�(sh霉)鎿�(j霉)鎺ュ彛:骞惰伅(li谩n) 杞夋彌鍣ㄦ暩(sh霉)鐩�:1 鍔熺巼鑰楁暎锛堟渶澶э級:1.82W 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:48-LQFP 渚涙噳鍟嗚ō鍌欏皝瑁�:48-LQFP锛�7x7锛� 鍖呰:绠′欢 杓稿叆鏁�(sh霉)鐩拰椤炲瀷:2 鍊嬪柈绔�锛屽柈妤�
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