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參數(shù)資料
| 型號： | ISL25700FRUZ-TK |
| 廠商： | Intersil |
| 文件頁數(shù)： | 13/18頁 |
| 文件大小： | 441K |
| 描述： | IC TEMP SWITCH MFET DRVR 10TQFN |
| 標準包裝： | 1,000 |
| 功能： | 溫度監(jiān)控系統(tǒng)（傳感器），溫度開關 |
| 傳感器類型： | 外部 |
| 感應溫度： | 40°C ~ 110°C 跳變點 |
| 精確度： | ±3°C |
| 拓撲： | 比較器，電壓基準 |
| 輸出類型： | 電壓 |
| 輸出警報： | 無 |
| 輸出風扇： | 無 |
| 電源電壓： | 3 V ~ 15 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-UFQFN |
| 供應商設備封裝： | 10-UTQFN（2.1x1.6） |
| 包裝： | 帶卷 (TR) |
ISL25700
13
FN6885.0
September 3, 2010
DAC Enable and Gain Control (Reg.03h [7:6])
When the DAC Enable bit, Reg.03h[7], is 0, the DAC output
is disabled, regardless of Reg.04h settings. When DAC
Enable bit is 1, the DAC output depends on the settings of
the DAC Gain bit Reg.03[6] and Reg.04h[7:0].
When the DAC Gain bit, Reg.03h[6], is 0, the DAC output
range is from 0V to 2V, i.e. Gain = 1. When the DAC Gain
bit is 1, the DAC output range is from 0V to 4V, i.e.
Gain = 2.
General Purpose DAC Register (Reg.04h [7:0])
This 8-bit register writes directly to the GP DAC to set the
output voltage. The default setting of this register is 80h.
The DAC output depends on the Gain setting in Reg.03h[6].
General Purpose Registers (Reg.05h and
Reg.06h)
These 8-bit General Purpose non-volatile and volatile
registers can be used for application specific purposes.
For example, they can be used to store calibration data
or other valuable system information.
R
INT
Absolute Error Register (Reg.07h [7:0])
This register contains the difference between the nominal
value and the real value of the internal resistor R
INT
. The
nominal value of this resistor is 9k and the voltage drop
on this resistor represents the temperature setpoint. The
LSB weight of the R
INT
absolute error is 15? Refer to
Equation 2 for calculation of R
INT
.
Control/Status Register (Reg.08h [7:0])
The setting of the
NV bit, Reg.08h[7], determines if data
is to be read or written to the non-volatile and/or volatile
memory. When this bit is 0, all operation will be targeted
to non-volatile memory, and the data will be copied to
volatile memory simultaneously. When this bit is 1, all
operation will be targeted to the volatile memory only.
The default setting of the
NV bit is 0.
The Busy bit, Reg.08h[0], is a read only bit. When 1 is
read from this bit, it indicates that the non-volatile cycle
is in progress. Reading from this bit eliminates getting a
NACK if the host attempts to write to the non-volatile
memory before the previous data is stored.
I
2
C Serial Interface
The ISL25700 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as
the receiver. The device controlling the transfer is a
master and the device being controlled is the slave. The
master always initiates data transfers and provides the
clock for both transmit and receive operations.
Therefore, the ISL25700 operates as a slave device in all
applications.
All communication over the I
2
C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (see
Figure 13). On power-up of the ISL25700, the SDA pin is
in the input mode.
All I
2
C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH. The ISL25700 continuously monitors
the SDA and SCL lines for the START condition and does
not respond to any command until this condition is met
(see Figure 13). A START condition is ignored during the
power-up sequence and during internal non-volatile write
cycles.
All I
2
C interface operations must be terminated by a
STOP condition, which is a LOW to HIGH transition of
SDA while SCL is HIGH (see Figure 13). A STOP condition
at the end of a read operation, or at the end of a write
operation to volatile bytes, only places the device in its
standby mode. A STOP condition during a write operation
to a non-volatile byte initiates an internal non-volatile
write cycle. The device enters its standby state when the
internal non-volatile write cycle is completed.
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting
device, either master or slave, releases the SDA bus
after transmitting 8 bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the 8 bits of data (see Figure 14).
The ISL25700 responds with an ACK after recognition of
a START condition, followed by a valid Identification Byte,
and once again after successful receipt of an Address
Byte. The ISL25700 also responds with an ACK after
receiving a Data Byte of a write operation. The master
must respond with an ACK after receiving a Data Byte of
a read operation.
A valid Identification Byte contains 0101000 in seven MSBs.
The LSB is the Read/
W
rite bit. Its value is 1 for a Read
operation and 0 for a Write operation (see Table 5).
TABLE 5. IDENTIFICATION BYTE FORMAT
0
1
0
1
0
0
0
R/
W
(MSB)
(LSB)
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