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參數(shù)資料
| 型號： | ISL1221IUZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC LP BATT BACK SRAM 10MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Solutions for Industrial Control Applications |
| 標(biāo)準(zhǔn)包裝： | 980 |
| 類型： | 時間事件記錄器 |
| 特點： | 警報器，閏年，SRAM |
| 存儲容量： | 2B |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 管件 |
17
FN6316.1
July 15, 2010
Note: xx indicate other control bits
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30am on January 1 (after
seconds changes from 59 to 00) by setting the ALM bit in the
status register to “1” and also bringing the IRQ output low.
Example 2 – Pulsed interrupt once per minute (IM = “1”)
Interrupts at one minute intervals when the seconds register
is at 30 seconds.
A. Set Alarm registers as follows:
B. Set the Interrupt register as follows:
Note: xx indicate other control bits
Once the registers are set, the following waveform will be
seen at IRQ-:
Note that the status register ALM bit will be set each time the
alarm is triggered, but does not need to be read or cleared.
User Registers
Addresses [12h to 13h]
These registers are 2 bytes of battery-backed user memory
storage.
Time Stamp Registers
Addresses [14h to 19h]
These registers contain the time stamp information in a similar
format to the RTC registers. When a valid Event is triggered at
the EVIN pin (low to high transition), these registers record the
values from the RTC registers. At the same time the EVT bit is
set and the EVDET- pin changes state (if it is enabled). The six
registers include second, minute, hour, date, month and year of
the event. Day of week is not recorded as it is not normally
required and is arbitrarily set.
Only the first Event in a series of events is time stamped, all
subsequent events are ignored. The current time stamp is
retained until the EVT bit is cleared and the next Event
occurs (EVIN pin is triggered). The contents of these
registers are cleared only after full power cycling.
I2C Serial Interface
The ISL1221 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is the master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL1221
operates as a slave device in all applications.
All communication over the I2C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (see
Figure 14). On power up of the ISL1221, the SDA pin is in
the input mode.
All I2C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL1221 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (see
Figure 14). A START condition is ignored during the
power-up sequence.
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (see Figure 14). A STOP condition at the end
of a read operation or at the end of a write operation to
memory only places the device in its standby mode.
An acknowledge (ACK) is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (see Figure 15).
The ISL1221 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL1221 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
ALARM
REGISTER
BIT
DESCRIPTION
76543210 HEX
SCA
10110000 B0h Seconds set to 30,
enabled
MNA
00000000 00h Minutes disabled
HRA
00000000 00h Hours disabled
DTA
00000000 00h Date disabled
MOA
00000000 00h Month disabled
DWA
00000000 00h Day of week disabled
CONTROL
REGISTER
BIT
DESCRIPTION
76543210 HEX
INT
1 1 x x 0000 x0hEnable Alarm and Int
Mode
60 SEC
RTC AND ALARM REGISTERS ARE BOTH “30” SEC
ISL1221
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