- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄2001 > ISL1221IUZ (Intersil)IC RTC LP BATT BACK SRAM 10MSOP PDF資料下載
參數(shù)資料
| 型號(hào)： | ISL1221IUZ |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 7/24頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC LP BATT BACK SRAM 10MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Solutions for Industrial Control Applications |
| 標(biāo)準(zhǔn)包裝： | 980 |
| 類(lèi)型： | 時(shí)間事件記錄器 |
| 特點(diǎn)： | 警報(bào)器，閏年，SRAM |
| 存儲(chǔ)容量： | 2B |
| 時(shí)間格式： | HH:MM:SS（12/24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 管件 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)當(dāng)前第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)
15
FN6316.1
July 15, 2010
NOTE: In order to use the sampling mode time-based hysteresis
must be activated. See Table 11.
EVENT INPUT TIME BASE HYSTERESIS SELECTION
BITS (EHYS<1:0>)
These two bits select the time base hysteresis of the EVIN
pin to filter bouncing or noise of external event detection
circuits. The time filter can be set between 0 to 31.25ms.
EVENT DETECT ENABLE BIT (EVEN)
This bit enables/disables the Event Detect function of the
ISL1221. When this bit is set to “1”, the Event Detect and
Time Stamp are active. When this bit is cleared to “0”, the
Event Detect and Time Stamp are disabled. Only the first
Event is Time Stamped in a series of Events between Event
resets (see EVT bit in the Status Register).
RTC HALT ON EVENT DETECT BIT (RTCHLT)
This bit sets the RTC registers to continue or halt counting
upon an Event Detect triggered by the EV pin. The time
keeping function will cease when RTCHLT is set to “1”, the
RTC will discontinue incrementing if an event is detected.
Counting will resume when there is a valid write to the RTC
registers (i.e. time set). The RTCHLT is cleared to “0” after
the write to the RTC registers.
Note: This function requires that the event detection is
enabled (see EVEN bit).
EVENT OUTPUT IN BATTERY MODE ENABLE BIT
(EVBATB)
This bit enables/disables the EVDET pin during battery
backup mode (i.e. VBAT pin supply ON). When the EVBATB
is set to “1”, the Event Detect Output is disabled in battery
backup mode. When the EVBATB is cleared to “0”, the Event
Detect output is enabled in battery backup mode.This
feature can be used to save power during battery mode.
EVENT CURRENT SOURCE ENABLE BIT (EVIENB)
This bit enables/disables the internal pullup current source
used for the EVIN pin. When the EVIENB bit is set to “1”, the
pullup current source is always disabled. When the EVIENB
bit is cleared to “0”, the pullup current source is enabled
(current source is approximately 1A).
Analog Trimming Register
ANALOG TRIMMING REGISTER (ATR<5:0>)
Six analog trimming bits,
ATR0 to ATR5, are provided in
order to adjust the on-chip load capacitance value for
frequency compensation of the RTC. Each bit has a different
weight for capacitance adjustment. For example, using a
Citizen CFS-206 crystal with different ATR bit combinations
provides an estimated ppm adjustment range from -34 to
+80ppm to the nominal frequency compensation. The
combination of analog and digital trimming can give up to -94
to +140ppm of total adjustment.
The effective on-chip series load capacitance, CLOAD,
ranges from 4.5pF to 20.25pF with a mid-scale value of
12.5pF (default). CLOAD is changed via two digitally
controlled capacitors, CX1 and CX2, connected from the X1
The effective series load capacitance is the combination of
CX1 and CX2:
For example, CLOAD(ATR=00000) = 12.5pF,
CLOAD(ATR=100000) = 4.5pF, and CLOAD(ATR=011111) =
20.25pF. The entire range for the series combination of load
capacitance goes from 4.5pF to 20.25pF in 0.25pF steps.
Note that these are typical values.
TABLE 10.
ESMP1
ESMP0
EVENT SAMPLING RATE
0
Always ON
01
2Hz
10
1Hz
11
1/4Hz
TABLE 11.
EHYS1
EHYS0
TIME BASE HYSTERESIS
0
0 (pull-up always on)
0
1
3.9ms
1
0
15.625ms
1
31.25ms
FIGURE 13. DIAGRAM OF ATR
CX1
X1
X2
CRYSTAL
OSCILLATOR
CX2
CX
16 b5
8b4 4 b3 2b2 1 b1 0.5b0 9
+
+
+
+
+
+
()pF
=
(EQ. 1)
CLOAD
1
CX1
-----------
1
CX2
-----------
+
-----------------------------------
=
CLOAD
16 b5
8 b4 4 b3 2 b2 1 b1 0.5 b0 9
+
+
+
+
+
+
2
-----------------------------------------------------------------------------------------------------------------------------
pF
=
ISL1221
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISL26134AVZ | IC ADC 24BIT SRL 80SPS 28TSSOP |
| ISL26319FVZ-T7A | IC ADC 12BIT SRL/SPI 16TSSOP |
| ISL26329FVZ | IC ADC 12BIT SPI/SRL 16-TSSOP |
| ISL2671286IBZ | IC ADC 12BIT SPI/SRL 20K 8SOIC |
| ISL26712IRTZ | IC ADC 12BIT SAR 1MSPS 8-TDFN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISL1221IUZ-T | 功能描述:實(shí)時(shí)時(shí)鐘 REAL TIME CLKRTC IN RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| ISL14010 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Low Jitter Clock Generators for Set-Top Box |
| ISL14010IRZ | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 REAL TIME CLKRTC 16LD 3X3 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| ISL14010IRZ-T | 功能描述:實(shí)時(shí)時(shí)鐘 REAL TIME CLKRTC 16LD 3X3 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| ISL14011 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Low Jitter Clock Generators for Set-Top Box |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。