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參數(shù)資料
| 型號： | ISL12032IVZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 23/26頁 |
| 文件大小： | 0K |
| 描述： | IC RTC LP BATT BACK SRAM 14TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Solutions for Industrial Control Applications |
| 標(biāo)準(zhǔn)包裝： | 960 |
| 類型： | 時間事件記錄器 |
| 特點： | 警報器，SRAM，涓流充電器 |
| 存儲容量： | 128B |
| 時間格式： | HH:MM:SS:hh（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 管件 |
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6
FN6618.3
May 5, 2011
tLOW
Clock LOW Time
Measured at the 30% of VDD
crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VDD
crossing.
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA
falling edge. Both crossing
70% of VDD.
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge
crossing 30% of VDD to SCL
falling edge crossing 70% of
VDD.
600
ns
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to
70% of VDD window, to SCL
rising edge crossing 30% of
VDD.
100
ns
tHD:DAT
Input Data Hold Time
From SCL falling edge
crossing 30% of VDD to SDA
entering the 30% to 70% of
VDD window.
0
900
ns
tSU:STO
STOP Condition Setup Time
From SCL rising edge
crossing 70% of VDD, to SDA
rising edge crossing 30% of
VDD.
600
ns
tHD:STO
STOP Condition Hold Time
From SDA rising edge to
SCL falling edge. Both
crossing 70% of VDD.
600
ns
tDH
Output Data Hold Time
From SCL falling edge
crossing 30% of VDD, until
SDA enters the 30% to 70%
of VDD window.
0
ns
tR
SDA and SCL Rise Time
From 30% to 70% of VDD.
20 + 0.1 x Cb
300
ns
tF
SDA and SCL Fall Time
From 70% to 30% of VDD.
20 + 0.1 x Cb
300
ns
Cb
Capacitive loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
RPU
SDA and SCL Bus Pull-up Resistor
Off-chip
Maximum is determined by
tR and tF.
For Cb = 400pF, max is about
2k
Ω.
For Cb = 40pF, max is about
15k
Ω
1
k
Ω
NOTES:
5. IRQ and FOUT Inactive.
6. VDD > VBAT +VBATHYS
7. Specified at TA =+25°C.
8. FSCL = 400kHz.
9. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
10. Parameter is not 100% tested.
11. VDD = 0V. IBAT increases at VDD voltages between 0.5V and 1.5V.
12. These are I2C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specification.
13. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
I2C Interface Specifications
Specifications apply for: VDD = 2.7V to 5.5V, TA = -40°C to +85°C, unless otherwise stated. Boldface limits
apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 13)
TYP
(Note 7)
MAX
(Note 13) UNITS
NOTES
ISL12032
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