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參數(shù)資料
| 型號(hào)： | ISL12032IVZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 14/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC LP BATT BACK SRAM 14TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Solutions for Industrial Control Applications |
| 標(biāo)準(zhǔn)包裝： | 960 |
| 類型： | 時(shí)間事件記錄器 |
| 特點(diǎn)： | 警報(bào)器，SRAM，涓流充電器 |
| 存儲(chǔ)容量： | 128B |
| 時(shí)間格式： | HH:MM:SS:hh（12/24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 管件 |
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21
FN6618.3
May 5, 2011
Example 1
Alarm set with single interrupt (IM = ”0”)
A single alarm will occur on January 1 at 11:30am.
Set Alarm registers as follows:
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30 a.m. on January 1 (after
seconds changes from 59 to 00) by setting the ALM0 bit in the
status register to “1” and also bringing the IRQ output LOW.
Example 2
Pulsed interrupt once per minute (IM = ”1”)
Interrupts at one minute intervals when the seconds
register is at 30 seconds.
Set Alarm registers as follows:
Once the registers are set, the following waveform will be
seen at IRQ:
Note that the status register ALM0 bit will be set each time
the alarm is triggered, but does not need to be read or
cleared.
Time Stamp VDD to Battery Registers (TSV2B)
The TSV2B section bytes are identical to the RTC register
section, except they do not extend beyond the Month. The
Time Stamp captures the FIRST VDD to Battery Voltage
transition time, and will not update upon subsequent events,
until cleared (only the first event is captured before clearing).
Set CLRTS = 1 to clear this register (Addr 11h, PWRVDD
register).
Time Stamp Battery to VDD Registers (TSB2V)
The Time Stamp Battery to VDD section bytes are identical
to the RTC section bytes, except they do not extend beyond
Month. The Time Stamp captures the LAST transition of
VBAT to VDD (only the last power up event of a series of
power up/down events is retained). Set CLRTS = 1 to clear
this register (Addr 11h, PWRVDD register).
Time Stamp Event Registers (TSEVT)
The TSEVT section bytes are identical to the RTC section
bytes, except they do not extend beyond the Month. The Time
Stamp captures the first event and the most recent three
events. The first event Time Stamp will not update until cleared.
All 4 Time Stamps are all cleared to “0” when writing the event
counter (0Bh) is set to “0”.
Note: The time stamp registers are cleared to all “0”,
including the month and day, which is different from the RTC
and alarm registers (those registers default to 01h). This is
the indicator that no time stamping has occurred since the
last clear or initial power-up. Once a time stamp occurs,
there will be a non-zero time stamp.
User Memory Registers (accessed by
using Slave Address 1010111x)
Addresses [00h to 7Fh]
These registers are 128 bytes of battery-backed user SRAM.
Writes to this section do not need to be proceeded by setting
the WRTC bit.
I2C Serial Interface
The ISL12032 supports a bi-directional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is the master
and the device being controlled is the slave. The master
always initiates data transfers and provides the clock for
both transmit and receive operations. Therefore, the
ISL12032 operates as a slave device in all applications.
All communication over the I2C interface is conducted by
sending the MSB of each byte of data first.
ALARM
REGISTER
BIT
DESCRIPTION
76
543210
HEX
SCA0
00
000000
00h
Seconds disabled
MNA0
10
110000
B0h Minutes set to 30,
enabled
HRA0
1
0
010001
91h
Hours set to 11,
enabled
DTA0
10
000001
81h
Date set to 1,
enabled
MOA0
10
000001
81h
Month set to 1,
enabled
DWA0
00
000000
00h
Day of week
disabled
ALARM
REGISTER
BIT
DESCRIPTION
76543210 HEX
SCA0
10110000 B0h Seconds set to 30,
enabled
MNA0
00000000 00h Minutes disabled
HRA0
00000000 00h Hours disabled
DTA0
00000000 00h Date disabled
MOA0
00000000 00h Month disabled
DWA0
00000000 00h Day of week disabled
60s
RTC AND ALARM REGISTERS ARE BOTH “30s”
FIGURE 5. IRQ WAVEFORM
ISL12032
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| ISL12032IVZ-T | 功能描述:實(shí)時(shí)時(shí)鐘 REAL TIME CLK W/ EEPROM 14LD RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| ISL12057 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Cost and Low Power I2C RTC Real Time Clock/Calendar |
| ISL12057IBZ | 功能描述:實(shí)時(shí)時(shí)鐘 REAL TIME CLK W/ ALARM DS1337 COMP RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| ISL12057IBZ-T | 功能描述:實(shí)時(shí)時(shí)鐘 REAL TIME CLK W/ ALARM DS1337 COMP RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| ISL12057IRUZ-T | 功能描述:實(shí)時(shí)時(shí)鐘 REAL TIME CLK W/ ALARM DS1337 COMP RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
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