V
參數(shù)資料
型號(hào): ISL12032IVZ
廠商: Intersil
文件頁(yè)數(shù): 22/26頁(yè)
文件大?。?/td> 0K
描述: IC RTC LP BATT BACK SRAM 14TSSOP
產(chǎn)品培訓(xùn)模塊: Solutions for Industrial Control Applications
標(biāo)準(zhǔn)包裝: 960
類型: 時(shí)間事件記錄器
特點(diǎn): 警報(bào)器,SRAM,涓流充電器
存儲(chǔ)容量: 128B
時(shí)間格式: HH:MM:SS:hh(12/24 小時(shí))
數(shù)據(jù)格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 2.7 V ~ 5.5 V
電壓 - 電源,電池: 1.8 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 14-TSSOP
包裝: 管件
5
FN6618.3
May 5, 2011
VTRKHYS
Trickle Charge ON-OFF Hysteresis
50
mV
IRQ/ACRDY/LV/EVDET (OPEN DRAIN OUTPUTS)
VOL
Output Low Voltage
VDD = 5V, IOL = 3mA
0.4
V
VDD = 2.7V, IOL = 1mA
0.4
V
FOUT (CMOS OUTPUT)
VOL
Output Low Voltage
IOH = 1mA
0.3 x VDD
V
VOH
Output High Voltage
0.7 x VDD
V
EVIN
IEVPU
EVIN Pull-up Current
VDD = 5.5V, VBAT = 3.0V
1.0
3.0
8.0
A
VDD = 0V, VBAT = 1.8V
100
600
nA
VIL
Input Low Voltage
0.3 x VDD
V
VIH
Input High Voltage
0.7 x VDD
V
IEVPD
EVIN Disabled Pull-down Current
VDD = 5.5V
200
nA
DC Operating Characteristics Specifications apply for: VDD = 2.7V to 5.5V, TA = -40°C to +85°C, unless otherwise stated. Boldface
limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
(Note 13)
TYP
(Note 7)
MAX
(Note 13)
UNITS
NOTES
Power-Down Timing Specifications apply for: V
DD = 2.7V to 5.5V, TA = -40°C to +85°C, unless otherwise stated. Boldface limits apply over
the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
(Note 13)
TYP
(Note 7)
MAX
(Note 13)
UNITS
NOTES
VDD SR-
VDD Negative Slew Rate
10
V/ms
I2C Interface Specifications
Specifications apply for: VDD = 2.7V to 5.5V, TA = -40°C to +85°C, unless otherwise stated. Boldface limits
apply over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 13)
TYP
(Note 7)
MAX
(Note 13) UNITS
NOTES
VIL
SDA and SCL Input Buffer LOW
Voltage
-0.3
0.3 x VDD
V
VIH
SDA and SCL Input Buffer HIGH
Voltage
0.7 x VDD
VDD + 0.3
V
Hysteresis
SDA and SCL Input Buffer
Hysteresis
0.05 x VDD
V
VOL
SDA Output Buffer LOW Voltage,
Sinking 3mA
VDD = 5V, IOL = 3mA
0.4
V
CPIN
SDA and SCL Pin Capacitance
TA = +25°C, f = 1MHz,
VDD =5V, VIN =0V,
VOUT =0V
10
pF
fSCL
SCL Frequency
400
kHz
tIN
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the
max spec is suppressed.
50
ns
tAA
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing
30% of VDD, until SDA exits
the 30% to 70% of VDD
window.
900
ns
tBUF
Time the Bus Must be Free Before
the Start of a New Transmission
SDA crossing 70% of VDD
during a STOP condition, to
SDA crossing 70% of VDD
during the following START
condition.
1300
ns
ISL12032
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