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參數(shù)資料
| 型號(hào)： | ISL12030IBZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 6/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC/CALENDAR EEPROM 8-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Solutions for Industrial Control Applications |
| 標(biāo)準(zhǔn)包裝： | 980 |
| 類型： | 時(shí)鐘/日歷 |
| 特點(diǎn)： | 警報(bào)器，夏令時(shí)，SRAM |
| 存儲(chǔ)容量： | 128B |
| 時(shí)間格式： | HH:MM:SS:hh（12/24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
14
FN6617.2
May 5, 2011
.
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL12030 responds with an ACK. At this time, the I2C
interface enters a standby state.
A multiple byte operation within a page is permitted. The
Address Byte must have the start address, and the data
bytes are sent in sequence after the address byte, with the
ISL12030 sending an ACK after each byte. The page write is
terminated with a STOP condition from the master. The
pages within the ISL12030 do not support wrapping around
for page read or write operations.
Read Operation
A Read operation consists of a three byte instruction
followed by one or more Data Bytes (see Figure 7). The
master initiates the operation issuing the following
sequence: a START, the Identification byte with the RW bit
set to “0”, an Address Byte, a second START, and a second
Identification byte with the RW bit set to “1”. After each of the
three bytes, the ISL12030 responds with an ACK. Then the
ISL12030 transmits Data Bytes as long as the master
responds with an ACK during the SCL cycle following the
eighth bit of each byte. The master terminates the read
operation (issuing a STOP condition) following the last bit of
the last Data Byte (see Figure 7).
The Data Bytes are from the memory location indicated by
an internal pointer. This pointers initial value is determined
by the Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the last memory location in a section or page,
the master should issue a STOP. Bytes that are read at
addresses higher than the last address in a section may be
erroneous.
FIGURE 6. SLAVE ADDRESS, WORD ADDRESS AND DATA
BYTES
SLAVE
ADDRESS BYTE
D7
D6
D5
D2
D4
D3
D1
D0
A0
A7
A2
A4
A3
A1
DATA BYTE
A6
A5
1
10
1
R/W
1
WORD ADDRESS
SIGNALS
FROM THE
MASTER
SIGNALS FROM
THE SLAVE
SIGNAL AT
SDA
S
T
A
R
T
IDENTIFICATION
BYTE WITH
R/W=0
ADDRESS
BYTE
A
C
K
A
C
K
0
S
T
O
P
A
C
K
1
IDENTIFICATION
BYTE WITH
R/W = 1
A
C
K
S
T
A
R
T
LAST READ
DATA BYTE
FIRST READ
DATA BYTE
A
C
K
10
1
1111
10
1
11 11
FIGURE 7. READ SEQUENCE (CSR SLAVE ADDRESS SHOWN)
ISL12030
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