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| 型號： | ADSP-2185NKSTZ-320 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 23/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 100LQFP |
| 標準包裝： | 1 |
| 系列： | ADSP-21xx |
| 類型： | 定點 |
| 接口： | 主機接口，串行端口 |
| 時鐘速率： | 80MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 80kB |
| 電壓 - 輸入/輸出： | 1.8V，2.5V，3.3V |
| 電壓 - 核心： | 1.80V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應商設備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
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ADSP-218xN
Rev. A
|
Page 3 of 48
|
August 2006
GENERAL DESCRIPTION
The ADSP-218xN series consists of six single chip microcom-
puters optimized for digital signal processing applications. The
high-level block diagram for the ADSP-218xN series members
appears on the previous page. All series members are pin-com-
patible and are differentiated solely by the amount of on-chip
SRAM. This feature, combined with ADSP-21xx code compati-
bility, provides a great deal of flexibility in the design decision.
Specific family members are shown in Table 1.
ADSP-218xN series members combine the ADSP-2100 family
base architecture (three computational units, data address gen-
erators, and a program sequencer) with two serial ports, a 16-bit
internal DMA port, a byte DMA port, a programmable timer,
Flag I/O, extensive interrupt capabilities, and on-chip program
and data memory.
ADSP-218xN series members integrate up to 256K bytes of on-
chip memory configured as up to 48K words (24-bit) of pro-
gram RAM, and up to 56K words (16-bit) of data RAM. Power-
down circuitry is also provided to meet the low power needs of
battery-operated portable equipment. The ADSP-218xN is
available in a 100-lead LQFP package and 144-ball BGA.
Fabricated in a high-speed, low-power, 0.18 μm CMOS process,
ADSP-218xN series members operate with a 12.5 ns instruction
cycle time. Every instruction can execute in a single pro-
cessor cycle.
The ADSP-218xN’s flexible architecture and comprehensive
instruction set allow the processor to perform multiple opera-
tions in parallel. In one processor cycle, ADSP-218xN series
members can:
Generate the next program address
Fetch the next instruction
Perform one or two data moves
Update one or two data address pointers
Perform a computational operation
This takes place while the processor continues to:
Receive and transmit data through the two serial ports
Receive and/or transmit data through the internal
DMA port
Receive and/or transmit data through the byte DMA port
Decrement timer
ARCHITECTURE OVERVIEW
The ADSP-218xN series instruction set provides flexible data
moves and multifunction (one or two data moves with a com-
putation) instructions. Every instruction can be executed in a
single processor cycle. The ADSP-218xN assembly language
uses an algebraic syntax for ease of coding and readability. A
comprehensive set of development tools supports program
development.
The functional block diagram is an overall block diagram of the
ADSP-218xN series. The processor contains three independent
computational units: the ALU, the multiplier/accumulator
(MAC), and the shifter. The computational units process 16-bit
data directly and have provisions to support multiprecision
computations. The ALU performs a standard set of arithmetic
and logic operations; division primitives are also supported. The
MAC performs single-cycle multiply, multiply/add, and multi-
ply/subtract operations with 40 bits of accumulation. The shifter
performs logical and arithmetic shifts, normalization, denor-
malization, and derive exponent operations.
The shifter can be used to efficiently implement numeric format
control, including multiword and block floating-point
representations.
The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu-
tational units. The sequencer supports conditional jumps,
subroutine calls, and returns in a single cycle. With internal
loop counters and loop stacks, ADSP-218xN series members
execute looped code with zero overhead; no explicit jump
instructions are required to maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and pro-
gram memory). Each DAG maintains and updates four address
pointers. Whenever the pointer is used to access data (indirect
addressing), it is post-modified by the value of one of four possi-
ble modify registers. A length value may be associated with each
pointer to implement automatic modulo addressing for
circular buffers.
Five internal buses provide efficient data transfer:
Program Memory Address (PMA) Bus
Program Memory Data (PMD) Bus
Data Memory Address (DMA) Bus
Data Memory Data (DMD) Bus
Result (R) Bus
Table 1. ADSP-218xN DSP Microcomputer Family
Device
Program Memory
(K words)
Data Memory
(K words)
ADSP-2184N
4
ADSP-2185N
16
ADSP-2186N
8
ADSP-2187N
32
ADSP-2188N
48
56
ADSP-2189N
32
48
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