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參數(shù)資料
| 型號(hào)： | ADSP-2185NKSTZ-320 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/48頁 |
| 文件大小： | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 100LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ADSP-21xx |
| 類型： | 定點(diǎn) |
| 接口： | 主機(jī)接口，串行端口 |
| 時(shí)鐘速率： | 80MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 80kB |
| 電壓 - 輸入/輸出： | 1.8V，2.5V，3.3V |
| 電壓 - 核心： | 1.80V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
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ADSP-218xN
Rev. A
|
Page 11 of 48
|
August 2006
Program Memory (Host Mode) allows access to all internal
memory. External overlay access is limited by a single external
address line (A0). External program execution is not available in
host mode due to a restricted data bus that is only 16 bits wide.
Data Memory
Data Memory (Full Memory Mode) is a 16-bit-wide space used
for the storage of data variables and for memory-mapped con-
trol registers. The ADSP-218xN series has up to 56K words of
Data Memory RAM on-chip. Part of this space is used by 32
memory-mapped registers. Support also exists for up to two 8K
external memory overlay spaces through the external data bus.
All internal accesses complete in one cycle. Accesses to external
memory are timed using the wait states specified by the DWAIT
register and the wait state mode bit.
Data Memory (Host Mode) allows access to all internal mem-
ory. External overlay access is limited by a single external
address line (A0).
Memory-Mapped Registers (New to the ADSP-218xM and
N series)
ADSP-218xN series members have three memory-mapped reg-
isters that differ from other ADSP-21xx Family DSPs. The slight
modifications to these registers (Wait State Control, Program-
mable Flag and Composite Select Control, and System Control)
provide the ADSP-218xN’s wait state and BMS control features.
Default bit values at reset are shown; if no value is shown, the bit
is undefined at reset. Reserved bits are shown on a grey field.
These bits should always be written with zeros.
I/O Space (Full Memory Mode)
ADSP-218xN series members support an additional external
memory space called I/O space. This space is designed to sup-
port simple connections to peripherals (such as data converters
and external registers) or to bus interface ASIC data registers.
I/O space supports 2048 locations of 16-bit wide data. The lower
eleven bits of the external address bus are used; the upper three
bits are undefined.
Two instructions were added to the core ADSP-2100 Family
instruction set to read from and write to I/O memory space. The
I/O space also has four dedicated three-bit wait state registers,
Table 4. PMOVLAY Bits
Processor
PMOVLAY
Memory
A13
A12– 0
ADSP-2184N
No Internal Overlay
Region
Not Applicable
ADSP-2185N
0
Internal Overlay
Not Applicable
ADSP-2186N
No Internal Overlay
Region
Not Applicable
ADSP-2187N
0, 4, 5
Internal Overlay
Not Applicable
ADSP-2188N
0, 4, 5, 6, 7
Internal Overlay
Not Applicable
ADSP-2189N
0, 4, 5
Internal Overlay
Not Applicable
All Processors
1
External Overlay 1
0
13 LSBs of Address Between 0x2000 and 0x3FFF
All Processors
2
External Overlay 2
1
13 LSBs of Address Between 0x2000 and 0x3FFF
Table 5. DMOVLAY Bits
Processor
DMOVLAY
Memory
A13
A12– 0
ADSP-2184N
No Internal Overlay Region
Not Applicable
ADSP-2185N
0
Internal Overlay
Not Applicable
ADSP-2186N
No Internal Overlay Region
Not Applicable
ADSP-2187N
0, 4, 5
Internal Overlay
Not Applicable
ADSP-2188N
0, 4, 5, 6, 7, 8
Internal Overlay
Not Applicable
ADSP-2189N
0, 4, 5, 6, 7
Internal Overlay
Not Applicable
All Processors
1
External Overlay 1
0
13 LSBs of Address
Between 0x0000 and
0x1FFF
All Processors
2
External Overlay 2
1
13 LSBs of Address
Between 0x0000 and
0x1FFF
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