參數(shù)資料
型號: ADSP-2185NKSTZ-320
廠商: Analog Devices Inc
文件頁數(shù): 31/48頁
文件大?。?/td> 0K
描述: IC DSP CONTROLLER 16BIT 100LQFP
標準包裝: 1
系列: ADSP-21xx
類型: 定點
接口: 主機接口,串行端口
時鐘速率: 80MHz
非易失內存: 外部
芯片上RAM: 80kB
電壓 - 輸入/輸出: 1.8V,2.5V,3.3V
電壓 - 核心: 1.80V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應商設備封裝: 100-LQFP(14x14)
包裝: 托盤
ADSP-218xN
Rev. A
|
Page 37 of 48
|
August 2006
IDMA Read, Long Read Cycle
Table 24. IDMA Read, Long Read Cycle
Parameter
Min
Max
Unit
Timing Requirements:
tIKR
IACK Low Before Start of Read1
0ns
tIRK
End of read After IACK Low2
2ns
Switching Characteristics:
tIKHR
IACK High After Start of Read
10
ns
tIKDS
IAD15 – 0 Data Setup Before IACK Low
0.5tCK – 3
ns
tIKDH
IAD15 – 0 Data Hold After End of Read
0ns
tIKDD
IAD15 – 0 Data Disabled After End of Read2
10
ns
tIRDE
IAD15 – 0 Previous Data Enabled After Start of Read
0
ns
tIRDV
IAD15 – 0 Previous Data Valid After Start of Read
11
ns
tIRDH1
IAD15 – 0 Previous Data Hold After Start of Read (DM/PM1)
3
2tCK – 5
ns
tIRDH2
IAD15 – 0 Previous Data Hold After Start of Read (PM2)
4
tCK – 5
ns
1 Start of Read = IS Low and IRD Low.
2 End of Read = IS High or IRD High.
3 DM read or first half of PM read.
4 Second half of PM read.
Figure 35. IDMA Read, Long Read Cycle
tIRK
tIKR
PREVIOUS
DATA
READ
DATA
tIKHR
tIKDS
tIRDV
tIKDD
tIRDE
tIKDH
IAD15–0
IACK
IS
IRD
tIRDH1 OR tIRDH2
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