參數(shù)資料
型號： ADSP-2185NKSTZ-320
廠商： Analog Devices Inc
文件頁數(shù)： 19/48頁
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 16BIT 100LQFP
標(biāo)準(zhǔn)包裝： 1
系列： ADSP-21xx
類型： 定點(diǎn)
接口： 主機(jī)接口，串行端口
時鐘速率： 80MHz
非易失內(nèi)存： 外部
芯片上RAM： 80kB
電壓 - 輸入/輸出： 1.8V，2.5V，3.3V
電壓 - 核心： 1.80V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 托盤
Rev. A
|
Page 26 of 48
|
August 2006
ADSP-218xN
TIMING SPECIFICATIONS
This section contains timing information for the DSP’s
external signals.
General Notes
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently,
parameters cannot be added up meaningfully to derive
longer times.
Timing Notes
Switching characteristics specify how the processor changes its
signals. Designers have no control over this timing—circuitry
external to the processor must be designed for compatibility
with these signal characteristics. Switching characteristics tell
what the processor will do in a given circumstance. Switching
characteristics can also be used to ensure that any timing
requirement of a device connected to the processor (such as
memory) is satisfied.
Timing requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Frequency Dependency For Timing Specifications
tCK is defined as 0.5 tCKI. The ADSP-218xN uses an input clock
with a frequency equal to half the instruction rate. For example,
a 40 MHz input clock (which is equivalent to 25 ns) yields a
12.5 ns processor cycle (equivalent to 80 MHz). tCK values
within the range of 0.5 tCKI period should be substituted for all
relevant timing parameters to obtain the specification value.
Example: tCKH = 0.5 tCK – 2 ns = 0.5 (12.5 ns) – 2 ns = 4.25 ns
Output Drive Currents
Figure 21 shows typical I-V characteristics for the output driv-
ers on the ADSP-218xN series.The curves represent the current
drive capability of the output drivers as a function of
output voltage.
Figure 23 shows the typical power-down supply current.
Capacitive Loading
Figure 24 and Figure 25 show the capacitive loading characteris-
tics of the ADSP-218xN.
Figure 21. Typical Output Driver Characteristics
for VDDEXT at 3.6 V, 3.3 V, 2.5 V, and 1.8 V
V OL
SOURCE VOLTAGE – V
00.5
1.0
S
O
U
R
C
E
C
U
R
E
N
T
–
m
A
60
0
–20
–40
–60
40
20
VDDEXT =3.6V@ –40 C
VDDEXT =3.3V@ +25 C
VDDEXT = 1.8/2.5V @ +85 C
VDDEXT =2.5V @ +85 C
V DDEXT = 3.6 V @ –40 C
80
–80
1.5
2.0
2.5
3.0
3.5
4.0
VDDEXT = 1.8/2.5V @ +85 C
V
OH
VDDEXT =3.3V @ +25 C
VDDEXT =1.8V @ +85 C
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