VDD > VBAT
參數(shù)資料
型號(hào): ISL12028IB27Z
廠商: Intersil
文件頁(yè)數(shù): 9/29頁(yè)
文件大?。?/td> 0K
描述: IC RTC W/EEPROM 2.7V 14SOIC
產(chǎn)品培訓(xùn)模塊: Solutions for Industrial Control Applications
標(biāo)準(zhǔn)包裝: 1,000
類型: 時(shí)鐘/日歷
特點(diǎn): 警報(bào)器,閏年,監(jiān)控器,監(jiān)視計(jì)時(shí)器
時(shí)間格式: HH:MM:SS(12/24 小時(shí))
數(shù)據(jù)格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 2.7 V ~ 5.5 V
電壓 - 電源,電池: 1.8 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 14-SOICN
包裝: 管件
17
FN8233.9
November 30, 2010
VDD > VBAT +VBATHYS
The Legacy Mode power control conditions are illustrated in
Figure 15.
Power On Reset
Application of power to the ISL12028 activates a Power On
Reset Circuit that pulls the RESET pin active. This signal
provides several benefits.
- It prevents the system microprocessor from starting to
operate with insufficient voltage.
- It prevents the processor from operating prior to
stabilization of the oscillator.
- It allows time for an FPGA to download its configuration
prior to initialization of the circuit.
- It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power-up.
When VDD exceeds the device VRESET threshold value for
typically 250ms the circuit releases RESET, allowing the
system to begin operation. Recommended slew rate is
between 0.2V/ms and 50V/ms.
NOTE: If the VBAT voltage drops below the data sheet
minimum of 1.8V and the VDD power cycles to 0V then back
to VDD voltage, then the RESET output may stay low and the
I2C communications will not operate. The VBAT and VDD
power will need to be cycled to 0V together to allow normal
operation again.
Watchdog Timer Operation
The watchdog timer time-out period is selectable. By writing
a value to WD1 and WD0, the Watchdog timer can be set
to 3 different time-out periods or off. When the Watchdog
timer is set to off, the Watchdog circuit is configured for low
power operation. See Table 8.
Watchdog Timer Restart
The Watchdog Timer is started by a falling edge of SDA
when the SCL line is high (START condition). The start
signal restarts the Watchdog timer counter, resetting the
period of the counter back to the maximum. If another
START fails to be detected prior to the Watchdog timer
expiration, then the RESET pin becomes active for one reset
time out period. In the event that the start signal occurs
during a reset time out period, the start will have no effect.
When using a single START to refresh Watchdog timer, a
STOP condition should be followed to reset the device back
to stand-by mode (see Figure 3).
In battery mode, the Watchdog timer function is disabled.
Low Voltage Reset (LVR) Operation
When a power failure occurs, a voltage comparator
compares the level of the VDD line versus a preset threshold
voltage (VRESET), then generates a RESET pulse if it is
below VRESET. The reset pulse will time-out 250ms after the
VDD line rises above VRESET. If the VDD remains below
VRESET, then the RESET output will remain asserted low.
Power-up and power-down waveforms are shown in
Figure 4 on page 7. The LVR circuit is to be designed so the
RESET signal is valid down to VDD = 1.0V.
When the LVR signal is active, unless the part has been
switched into the battery mode, the completion of an
in-progress non-volatile write cycle is unaffected, allowing a
non-volatile write to continue as long as possible (down to
the Reset Valid Voltage). The LVR signal, when active, will
terminate any in-progress communications to the device and
prevents new commands from disrupting any current write
In battery mode, the RESET signal output is asserted LOW
when the VDD voltage supply has dipped below the VRESET
threshold. The RESET signal output will not return HIGH
until the device is back to VDD mode even the VDD voltage is
above VRESET threshold.
Serial Communication
The device supports the I2C bidirectional serial bus protocol.
CLOCK AND DATA
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions (see Figure 16).
START CONDITION
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
start condition and will not respond to any command until
this condition has been met (see Figure 17).
STOP CONDITION
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is
HIGH. The stop condition is also used to place the device
into the Standby power mode after a read sequence. A stop
TABLE 8. WATCHDOG TIMER OPERATION
WD1
WD0
DURATION
1
disabled
1
0
250ms
0
1
750ms
0
1.75s
VBAT
IN
VOLTAGE
VDD
ON
OFF
FIGURE 15. BATTERY SWITCHOVER IN LEGACY MODE
ISL12028, ISL12028A
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