參數(shù)資料
型號： ISL12026IBZ-T7A
廠商： Intersil
文件頁數(shù)： 2/24頁
文件大?。?/td> 0K
描述： IC RTC/CALENDAR EEPROM 8SOIC
標準包裝： 250
類型： 時鐘/日歷
特點： 警報器，閏年
時間格式： HH:MM:SS（12/24 小時）
數(shù)據(jù)格式： YY-MM-DD-dd
接口： I²C，2 線串口
電源電壓： 2.7 V ~ 5.5 V
電壓 - 電源，電池： 1.8 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SOIC
包裝： 帶卷 (TR)
10
FN8231.9
November 30, 2010
Alarm Registers (Non-Volatile)
Alarm0 and Alarm1
The alarm register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (seconds, minutes, etc.) are used to make
the comparison. Note that there is no alarm byte for year.
The alarm function works as a comparison between the
alarm registers and the RTC registers. As the RTC
advances, the alarm will be triggered once a match occurs
between the alarm registers and the RTC registers. Any one
alarm register, multiple registers, or all registers can be
enabled for a match. See “Device Operation” on page 12
and “Application Section” on page 19 for more information.
Control Registers (Non-Volatile)
The Control Bits and Registers described in the following are
non-volatile.
BL Register
BP2, BP1, BP0 - Block Protect Bits
The Block Protect Bits, BP2, BP1 and BP0, determine which
blocks of the array are write protected. A write to a protected
block of memory is ignored. The block protect bits will prevent
write operations to one of eight segments of the array. The
partitions are described in Table 3.
TABLE 2. CLOCK/CONTROL MEMORY MAP
ADDR.
TYPE
REG NAME
BIT
RANGE
ISL12
026
DEF
AUL
T
ISL1202
6
A
DEF
AUL
T
76
5
4
3
2
1
0
003F
Status
SR
BAT
AL1
AL0
OSCF
0
RWEL
WEL
RTCF
01h
0037
RTC
(SRAM)
Y2K
0
Y2K21
Y2K20
Y2K13
0
Y2K10
19/20
20h
0036
DW
0
DY2
DY1
DY0
0-6
00h
0035
YR
Y23
Y22
Y21
Y20
Y13
Y12
Y11
Y10
0-99
00h
0034
MO
0
G20
G13
G12
G11
G10
1-12
00h
0033
DT
0
D21
D20
D13
D12
D11
D10
1-31
01h
0032
HR
MIL
0
H21
H20
H13
H12
H11
H10
0-23
00h
0031
MN
0
M22
M21
M20
M13
M12
M11
M10
0-59
00h
0030
SC
0
S22
S21
S20
S13
S12
S11
S10
0-59
00h
0014
Control
(EEPROM)
PWR
SBIB
BSW
0
40h
00h
0013
DTR
0
DTR2
DTR1
DTR0
00h
0012
ATR
0
ATR5
ATR4
ATR3
ATR2
ATR1
ATR0
00h
0011
INT
IM
AL1E
AL0E
FO1
FO0
0
00h
0010
BL
BP2
BP1
BP0
0
00h
000F
Alarm1
(EEPROM)
Y2K1
0
A1Y2K21
A1Y2K20
A1Y2K13
0
A1Y2K10
19/20
20h
000E
DWA1
EDW1
0
DY2
DY1
DY0
0-6
00h
000D
YRA1
Unused - Default = RTC Year value (No EEPROM) - Future expansion
000C
MOA1
EMO1
0
A1G20
A1G13
A1G12
A1G11
A1G10
1-12
00h
000B
DTA1
EDT1
0
A1D21
A1D20
A1D13
A1D12
A1D11
A1D10
1-31
00h
000A
HRA1
EHR1
0
A1H21
A1H20
A1H13
A1H12
A1H11
A1H10
0-23
00h
0009
MNA1
EMN1
A1M22
A1M21
A1M20
A1M13
A1M12
A1M11
A1M10
0-59
00h
0008
SCA1
ESC1
A1S22
A1S21
A1S20
A1S13
A1S12
A1S11
A1S10
0-59
00h
0007
Alarm0
(EEPROM)
Y2K0
0
A0Y2K21
A0Y2K20
A0Y2K13
0
A0Y2K10
19/20
20h
0006
DWA0
EDW0
0
DY2
DY1
DY0
0-6
00h
0005
YRA0
Unused - Default = RTC Year value (No EEPROM) - Future expansion
0004
MOA0
EMO0
0
A0G20
A0G13
A0G12
A0G11
A0G10
1-12
00h
0003
DTA0
EDT0
0
A0D21
A0D20
A0D13
A0D12
A0D11
A0D10
1-31
00h
0002
HRA0
EHR0
0
A0H21
A0H20
A0H13
A0H12
A0H11
A0H10
0-23
00h
0001
MNA0
EMN0
A0M22
A0M21
A0M20
A0M13
A0M12
A0M11
A0M10
0-59
00h
0000
SCA0
ESC0
A0S22
A0S21
A0S20
A0S13
A0S12
A0S11
A0S10
0-59
00h
ISL12026, ISL12026A
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