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1259
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
47.18 Peripheral Timings
47.18.1 SPI
47.18.1.1 Maximum SPI Frequency
The following formulas give maximum SPI frequency in Master read and write modes and in Slave read and write modes.
Master Write Mode
The SPI is only sending data to a slave device such as an LCD, for example. The limit is given by SPI2 (or SPI5)
timing. Since it gives a maximum frequency above the maximum pad speed (see
Section 47.10 “I/Os”), the maxi-
mum SPI frequency is the one from the pad.
Master Read Mode
tvalid is the slave time response to output data after deleting an SPCK edge. For Atmel SPI DataFlash
(AT45DB642D), tvalid (or tv ) is 12 ns Max.
This gives fSPCKMax = 39 MHz @ VDDIO = 3.3V.
Slave Read Mode
In slave mode, SPCK is the input clock for the SPI. The max SPCK frequency is given by setup and hold timings
SPI7/SPI8(or SPI10/SPI11). Since this gives a frequency well above the pad limit, the limit in slave read mode is
given by SPCK pad.
Slave Write Mode
tsetup is the setup time from the master before sampling data (12 ns).
This gives fSPCKMax = 39 MHz @ VDDIO = 3.3V.
47.18.1.2 Timing Conditions
Timings are given assuming a capacitance load on MISO, SPCK and MOSI:
47.18.1.3 Timing Extraction
Figure 47-9. SPI Master mode 1 and 2
f
SPCKMax
1
SPI
0 or SPI3
() t
valid
+
----------------------------------------------------------
=
f
SPCKMax
1
SPI
6 or SPI9
() t
setup
+
------------------------------------------------------------
=
Table 47-37. Capacitance Load for MISO, SPCK and MOSI (product dependent)
Supply
Corner
Max
Min
3.3V
40 pF
5 pF
1.8V
20 pF
5 pF
SPCK
MISO
MOSI
SPI2
SPI0
SPI1