133
AT90PWM216/316 [DATASHEET]
7710H–AVR–07/2013
The PSC output period is directly equal to the PSCOUTn0 On Time + Dead Time (OT0+DT0) and PSCOUTn1 On
Time + DeadTime (OT1+DT1) values. These values are 12 bits numbers. The frequency adjustment can only be
done in steps like the dedicated counters. The step width is defined as the frequency difference between two
neighboring PSC frequencies:
with k is the number of CLK
PSC period in a PSC cycle and is given by the following formula:
with f
OP is the output operating frequency.
example, in normal mode, with maximum operating frequency 160 kHz and f
PLL = 64MHz, k equals 400. The result-
ing resolution is Delta F equals 64MHz / 400 / 401 = 400 Hz.
In enhanced mode, the output frequency is the average of the frame formed by the 16 consecutive cycles.
f
b1 and fb2 are two neighboring base frequencies.
Then the frequency resolution is divided by 16. In the example above, the resolution equals 25 Hz.
15.7.1
Frequency distribution
The frequency modulation is done by switching two frequencies in a 16 consecutive cycle frame. These two fre-
quencies are f
b1 and fb2 where fb1 is the nearest base frequency above the wanted frequency and fb2 is the nearest
base frequency below the wanted frequency. The number of f
b1 in the frame is (d-16) and the number of fb2 is d.
The f
b1 and fb2 frequencies are evenly distributed in the frame according to a predefined pattern. This pattern can
be as given in the following table or by any other implementation which give an equivalent evenly distribution.
ff1 f2
–
f
PLL
k
----------
f
PLL
k
1
+
------------
–
f
PSC
1
kk
1
+
--------------------
==
=
n
f
PSC
f
OP
----------
=
f
AVERAGE
16
d
–
16
---------------
f
b1
d
16
------
f
b2
+
=
f
AVERAGE
16
d
–
16
---------------
f
PLL
n
----------
d
16
------
f
PLL
n
1
+
------------
+
=