194
AT90PWM216/316 [DATASHEET]
7710H–AVR–07/2013
Bit 0 – TXB8: Transmit Data Bit 8
TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits.
Must be written before writing the low bits to UDR.
When the EUSART mode is enable and configured in 17 bits transmit mode, this bit contains the seventeenth bit
(See EUSART section).
17.10.4
USART Control and Status Register C – UCSRC
Bit 7 – Reserved Bit
This bit is reserved for future use. For compatibilty with future devices, this bit must be written to zero when
USCRC is written.
Bit 6 – UMSEL: USART Mode Select
This bit selects between asynchronous and synchronous mode of operation.
When configured in EUSART mode, the synchronous mode should not be set with Manchester mode (See
EUSART section).
Bit 5:4 – UPM1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically gener-
ate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for
the incoming data and compare it to the UPM setting. If a mismatch is detected, the UPE Flag in UCSRA will be
set.
This setting is available in EUSART mode only when data bits are level encoded (in Manchester the parity checker
and generator are not available).
Bit 3 – USBS: Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting.
Bit
76543210
-
UMSEL0
UPM1
UPM0
USBS
UCSZ1
UCSZ0
UCPOL
UCSRC
Read/Write
R/W
Initial Value
00000110
Table 17-4.
UMSEL Bit Settings
UMSEL
Mode
0
Asynchronous Operation
1
Synchronous Operation
Table 17-5.
UPM Bits Settings
UPM1
UPM0
Parity Mode
0
Disabled
01
Reserved
1
0
Enabled, Even Parity
1
Enabled, Odd Parity