230
AT90PWM216/316 [DATASHEET]
7710H–AVR–07/2013
a.
Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground
plane, and keep them well away from high-speed switching digital tracks.
b.
The AV
CC pin on the device should be connected to the digital VCC supply voltage via an LC network
c.
Use the ADC noise canceler function to reduce induced noise from the CPU.
d.
If any ADC port pins are used as digital outputs, it is essential that these do not switch while a conver-
sion is in progress.
Figure 20-9. ADC Power Connections
20.6.3
Offset Compensation Schemes
The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential measurements as much
as possible. The remaining offset in the analog path can be measured directly by shortening both differential inputs
then subtracted in software from the measurement results. Using this kind of software based offset correction, off-
set on any channel can be reduced below one LSB.
20.6.4
ADC Accuracy Definitions
An n-bit single-ended ADC converts a voltage linearly between GND and V
REF in 2
n steps (LSBs). The lowest code
is read as 0, and the highest code is read as 2
n-1.
Several parameters describe the deviation from the ideal behavior:
Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal
value: 0 LSB.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
GND
(ADC0) PE2
(ADC1) PD4
PB7(ADC4)
PB6 (ADC7)
PB5 (ADC6)
PC7 (D2A)
PB4 (AMP0+)
PB3 (AMP0-)
PC6 (ADC10/ACMP1)
AREF
AGND
AVCC
PC5 (ADC9/AMP1+)
PC4 (ADC8/AMP1-)
PB2 (ADC5)
PD7 (ACMP0)
PD6 (ADC3/ACMPM)
PD5 (ADC2/ACMP2)
100nF
Analog Ground Plane
10
μH