參數(shù)資料
型號(hào)： IS43R16800A1-5TL
廠商： INTEGRATED SILICON SOLUTION INC
元件分類： DRAM
英文描述： 8Meg x 16 128-MBIT DDR SDRAM
中文描述： 8M X 16 DDR DRAM, 0.65 ns, PDSO66
封裝： LEAD FREE, PLASTIC, TSOP2-66
文件頁(yè)數(shù)： 23/72頁(yè)
文件大?。?/td> 2174K
代理商： IS43R16800A1-5TL
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/17/06
23
ISSI
IS43R16800A1
Data from any Read burst may be truncated with a Burst Terminate command, as shown in timing figure entitled
Terminating a
Read Burst: CAS Latencies (Burst Length = 8)
. The Burst Terminate latency is equal to the read (CAS) latency, i.e.
the Burst Terminate command should be issued x cycles after the Read command, where x equals the number of desired data
element pairs.
Data from any Read burst must be completed or truncated before a subsequent Write command can be issued. If truncation is
necessary, the Burst Terminate command must be used, as shown in timing figure entitled
Read to Write: CAS Latencies (Burst
Length = 4 or 8)
. The example is shown for t
DQSS
(min). The t
DQSS
(max) case, not shown here, has a longer bus idle
time. t
DQSS
(min) and t
DQSS
(max) are defined in the section on Writes.
A Read burst may be followed by, or truncated with, a Precharge command to the same bank (provided that Auto Precharge
was not activated). The Precharge command should be issued x cycles after the Read command, where x equals the number of
desired data element pairs (pairs are required by the 2n prefetch architecture). This is shown in timing figure
Read to Pre-
charge: CAS Latencies (Burst Length = 4 or 8)
for Read latencies of 2 and 2.5. Following the Precharge command,
a subsequent command to the same bank cannot be issued until t
RP
is met. Note that part of the row precharge time is hidden
during the access of the last data elements.
In the case of a Read being executed to completion, a Precharge command issued at the optimum time (as described above)
provides the same operation that would result from the same Read burst with Auto Precharge enabled. The disadvantage of the
Precharge command is that it requires that the command and address busses be available at the appropriate time to issue the
command. The advantage of the Precharge command is that it can be used to truncate bursts.
相關(guān)PDF資料
PDF描述
IS43R32400A 4Meg x 32 128-MBIT DDR SDRAM
IS43R32400A-5B 4Meg x 32 128-MBIT DDR SDRAM
IS43R32400A-5BL 4Meg x 32 128-MBIT DDR SDRAM
IS43R32400A-6B 4Meg x 32 128-MBIT DDR SDRAM
IS43R32400A-6BI 4Meg x 32 128-MBIT DDR SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IS43R16800A-5T 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 128M 2.5v 8Mx16 400MHz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問(wèn)時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
IS43R16800A-5TL 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 128M 2.5v 8Mx16 400MHz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問(wèn)時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
IS43R16800A-5TL-TR 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 128M 2.5v 8Mx16 400MHz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問(wèn)時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
IS43R16800A-5T-TR 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 128M 2.5v 8Mx16 400MHz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問(wèn)時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
IS43R16800A-6 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:8Meg x 16 128-MBIT DDR SDRAM
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