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參數(shù)資料
| 型號(hào)： | IS42S32200 |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 為512k位× 32位× 4銀行（64兆位）同步動(dòng)態(tài)RAM |
| 文件頁數(shù)： | 33/55頁 |
| 文件大?。?/td> | 982K |
| 代理商： | IS42S32200 |
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IS42S32200
ISSI
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION
Rev. 00B
08/14/03
33
AC ELECTRICAL CHARACTERISTICS
(1,2,3)
-6
-7
Symbol
Parameter
Min.
Max.
Min.
Max.
Units
t
CK3
t
CK2
Clock Cycle Time
CAS
Latency = 3
CAS
Latency = 2
6
—
—
7
—
—
ns
ns
10
10
t
AC3
t
AC2
Access Time From CLK
(4)
CAS
Latency = 3
CAS
Latency = 2
—
—
5.5
7.5
—
—
6
8
ns
ns
t
CHI
CLK HIGH Level Width
2.5
—
3
—
ns
t
CL
CLK LOW Level Width
2.5
—
3
—
ns
t
OH
Output Data Hold Time
2
—
2.5
—
ns
t
LZ
Output LOW Impedance Time
1
—
1
—
ns
t
HZ3
t
HZ2
Output HIGH Impedance Time
(5)
CAS
Latency = 3
\—
—
5.5
7.5
—
—
5.5
8
ns
ns
CAS
Latency = 2
t
DS
Input Data Setup Time
1.5
—
2
—
ns
t
DH
Input Data Hold Time
1
—
1
—
ns
t
AS
Address Setup Time
1.5
—
2
—
ns
t
AH
Address Hold Time
1
—
1
—
ns
t
CKS
CKE Setup Time
1.5
—
2
—
ns
t
CKH
CKE Hold Time
1
—
1
—
ns
t
CKA
CKE to CLK Recovery Delay Time
1CLK+6
—
1CLK+7
—
ns
t
CS
Command Setup Time (
CS
,
RAS
,
CAS
,
WE
, DQM)
1.5
—
2
—
ns
t
CH
Command Hold Time (
CS
,
RAS
,
CAS
,
WE
, DQM)
1
—
1.75
—
ns
t
RC
Command Period (REF to REF / ACT to ACT)
60
—
70
—
ns
t
RAS
Command Period (ACT to PRE)
42
120,000
42
120,000
ns
t
RP
Command Period (PRE to ACT)
18
—
20
—
ns
t
RCD
Active Command To Read / Write Command Delay Time
18
—
20
—
ns
t
RRD
Notes:
1. An initial pause of 100us is required after power up, followed by two AUTO REFRESH commands, before proper device operation
is ensured. (Vcc and VccQ must be powered up simultaneously. GND and GNDQ must be at same potential.) The two AUTO
REFRESH command wake-ups should be repeated anytime the t
REF
refresh requirement is exceeded.
2. Measured with t
T
= 1 ns.
3. The reference level is 1.5V when measuring input signal timing. Rise/fall times are measured between V
IH
(min.) and V
IL
(max.).
4. Access time is measured at 1.5V with the load shown in the figure below.
5. The time t
HZ
(max.) is defined as the time required for the output voltage to transition by ± 200 mV from V
OH
(min.) or V
OL
(max.)
when the output is in the high impedance state.
6. CLK must be toggled a minimum of two times during this period.
Command Period (ACT [0] to ACT[1])
12
—
14
—
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS42S32200-6T | 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S32200-6TI | 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S32200-7T | 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S32200-7TI | 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S32400B-7TLI | 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS42S32200-6T | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S32200-6TI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S32200-7T | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S32200-7TI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S32200B | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
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