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參數資料
| 型號： | IS42S32200 |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 為512k位× 32位× 4銀行（64兆位）同步動態(tài)RAM |
| 文件頁數： | 11/55頁 |
| 文件大小： | 982K |
| 代理商： | IS42S32200 |
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IS42S32200
ISSI
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION
Rev. 00B
08/14/03
11
FUNCTIONAL DESCRIPTION
The 64Mb SDRAMs (512K x 32 x 4 banks) are quad-bank
DRAMs which operate at 3.3V and include a synchronous
interface (all signals are registered on the positive edge of
the clock signal, CLK). Each of the 16,777,216-bit banks
is organized as 2,048 rows by 256 columns by 32bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed
(BA0 and BA1 select the bank, A0-A10
select the row)
. The address bits
(A0-A7)
registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information covering
device initialization, register definition, command
descriptions and device operation.
Initialization
SDRAMs must be powered up and initialized in a
predefined manner.
The 64M SDRAM is initialized after the power is applied
to V
CC
and V
CCQ
(simultaneously) and the clock is stable.
A 100μs delay is required prior to issuing any command
other than a
COMMAND INHIBIT
or a
NOP
. The COMMAND
INHIBIT or NOP may be applied during the 100us period
and continue should at least through the end of the period.
With at least one COMMAND INHIBIT or NOP command
having been applied, a PRECHARGE command should be
applied once the 100μs delay has been satisfied. All
banks must be precharged. This will leave all banks in an
idle idle state where two
AUTO REFRESH
cycles must be
performed. After the
AUTO REFRESH
cycles are complete,
the SRDRAM is then ready for mode register programming.
The mode register should be loaded prior to applying any
operational command because it will power up in an
unknown state.
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| IS42S32200-6T | 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S32200-6TI | 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S32200-7T | 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S32200-7TI | 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S32400B-7TLI | 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| IS42S32200-6T | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S32200-6TI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S32200-7T | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S32200-7TI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S32200B | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
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