參數(shù)資料
型號(hào)： IS42S32200-7TI
廠商： INTEGRATED SILICON SOLUTION INC
元件分類： DRAM
英文描述： 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
中文描述： 2M X 32 SYNCHRONOUS DRAM, 6 ns, PDSO86
封裝： 0.400 INCH, TSOP2-86
文件頁(yè)數(shù)： 3/55頁(yè)
文件大?。?/td> 982K
代理商： IS42S32200-7TI
IS42S32200
ISSI
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION
Rev. 00B
08/14/03
3
PIN FUNCTIONS
Symbol
Pin No.
Type
Function (In Detail)
A0-A10
25 to 27
60 to 66
24
Input Pin
Address Inputs: A0-A10 are sampled during the ACTIVE
command (row-address A0-A10) and READ/WRITE command (A0-A7
with A10 defining auto precharge) to select one location out of the memory array
in the respective bank. A10 is sampled during a PRECHARGE command to
determine if all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
BA0, BA1
22,23
Input Pin
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ,
WRITE or PRECHARGE command is being applied.
CAS
18
Input Pin
CAS
, in conjunction with the
RAS
and
WE
, forms the device command. See the
"Command Truth Table" for details on device commands.
CKE
67
Input Pin
The CKE input determines whether the CLK input is enabled. The next rising edge
of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When
CKE is LOW, the device will be in either power-down mode, clock suspend mode,
or self refresh mode.
CKE is an
asynchronous i
nput.
CLK
68
Input Pin
CLK is the master clock input for this device. Except for CKE, all inputs to this
device are acquired in synchronization with the rising edge of this pin.
CS
20
Input Pin
The
CS
input determines whether command input is enabled within the device.
Command input is enabled when
CS
is LOW, and disabled with
CS
is HIGH. The
device remains in the previous state when
CS
is HIGH.
I/O0 to
I/O31
2, 4, 5, 7, 8, 10,11,13
74,76,77,79,80,82,83,85
45,47,48,50,51,53,54,56
31,33,34,36,37,39,40,42
I/O Pin
I/O0 to I/O15 are I/O pins. I/O through these pins can be controlled in byte units
using the DQM0-DQM3 pins
DQM0
DQM3
16,28,59,71
Input Pin
DQMx control thel ower and upper bytes of the I/O buffers. In read mode,
the output buffers are place in a High-Z state. During a WRITE cycle the input data
is masked. When DQMx is sampled HIGH and is an input mask signal for write
accesses and an output enable signal for read accesses. I/O0 through I/O7 are
controlled by DQM0. I/O8 throughI/O15 are controlled by DQM1. I/O16 through I/
O23 are controlled by DQM2. I/O24 through I/O31 are controlled by DQM3.
RAS
19
Input Pin
RAS
, in conjunction with
CAS
and
WE
, forms the device command. See the
"Command Truth Table" item for details on device commands.
WE
17
Input Pin
WE
, in conjunction with
RAS
and
CAS
, forms the device command. See the
"Command Truth Table" item for details on device commands.
V
CCQ
3,9,35,41,49,55,25,81
Supply Pin
V
CCQ
is the output buffer power supply.
V
CC
1,15,29,43
Supply Pin
V
CC
is the device internal power supply.
GND
Q
6,12,32,38,46,52,78,84
Supply Pin
GND
Q
is the output buffer ground.
GND
44,58,72,86
Supply Pin
GND is the device internal ground.
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IS42S32200B 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S32200B-6T 制造商:Integrated Silicon Solution Inc 功能描述:DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II
IS42S32200B-6TI 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S32200B-6TL 制造商:Integrated Silicon Solution Inc 功能描述:DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II
IS42S32200B-6TLI 制造商:Integrated Silicon Solution Inc 功能描述:DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II
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