參數(shù)資料
型號: IS42S16128-8T
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: Chassis Mount and Din Rail Filters RoHS Compliant: Yes
中文描述: 256K X 16 SYNCHRONOUS DRAM, 8 ns, PDSO50
封裝: 0.400 INCH, TSOP2-50
文件頁數(shù): 26/75頁
文件大?。?/td> 638K
代理商: IS42S16128-8T
26
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/13/00
IS42S16128
ISSI
A new read command can be executed while a write cycle
is in progress, i.e., before that cycle completes. Data
corresponding to the new read command is output after
the
CAS
latency has elapsed from the point the new read
command was executed. The I/On pins must be placed
in the HIGH impedance state at least one cycle before
data is output during this operation.
The interval (t
CCD
) between command must be at least
one clock cycle.
The selected bank must be set to the active state before
executing this command.
Interval Between Write and Read Commands
I/O
I/O
WRITE A0
READ B0
COMMAND
CLK
D
IN
A0
D
OUT
B0
D
OUT
B2
D
OUT
B1
D
OUT
B3
t
CCD
HI-Z
WRITE (CA=A, BANK 0)
READ (CA=B, BANK 0)
WRITE A0
READ B0
COMMAND
CLK
D
IN
A0
D
OUT
B0
D
OUT
B2
D
OUT
B1
D
OUT
B3
t
CCD
HI-Z
WRITE (CA=A, BANK 0)
READ (CA=B, BANK 0)
CAS
latency = 2, burst length = 4
CAS
latency = 3, burst length = 4
Don
t Care
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